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[
VHDL-FPGA-Verilog
]
husw
Description:
用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Platform:
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1024
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Author:
hsw0320
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Search - ModelSim xe III 6.3c
Search - ModelSim xe III 6.3c