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Description: 用于三级PC考试的重要资料,我花了好久才找到的,对于计算机等级考试的人非常重要-for three PC examination of the important information, I have spent a long time to find the computer for grading examinations were very important
Platform: |
Size: 92359 |
Author: wanglin |
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Description: SAM9261 BasicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating with a 100MHz Bus Clock. The rating is based on Dhrystone 2.1. It shows the rate when I+D Caches are disabled or enabled, with or without MMU and I Cache is disable or enabled, with or without MMU. -SAM9261 BasicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating w praxiology a 100MHz Bus Clock. The rating is based on Dhr ystone 2.1. It shows the rate when I Caches are d D. isabled or enabled, with or without MMU and I Cache is disable or enab led, with or without MMU.
Platform: |
Size: 424968 |
Author: 啊非 |
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Description: 用于三级PC考试的重要资料,我花了好久才找到的,对于计算机等级考试的人非常重要-for three PC examination of the important information, I have spent a long time to find the computer for grading examinations were very important
Platform: |
Size: 92160 |
Author: wanglin |
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Description: SAM9261 BasicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating with a 100MHz Bus Clock. The rating is based on Dhrystone 2.1. It shows the rate when I+D Caches are disabled or enabled, with or without MMU and I Cache is disable or enabled, with or without MMU. -SAM9261 BasicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating w praxiology a 100MHz Bus Clock. The rating is based on Dhr ystone 2.1. It shows the rate when I Caches are d D. isabled or enabled, with or without MMU and I Cache is disable or enab led, with or without MMU.
Platform: |
Size: 424960 |
Author: 啊非 |
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Description: Samsung S5PC100 Cortex A8 Users Manual , december 2009 , rev. 1.04
Platform: |
Size: 12106752 |
Author: Marius Cirsta |
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Description: 存储控制器，包括CPUside，接口，MEMORY side三个部分，使用verilog语言-This represents the "memory controller" It runs with the assumption that it is being connected to PC100 SDRAM.
Platform: |
Size: 8192 |
Author: AricSnow |
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Description: • PC100 functionality
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes Concurrent Auto
Precharge, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6μs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3-• PC100 functionality
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes Concurrent Auto
Precharge, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6μs/row)
• LVTTL-compatible inputs and outputs
• Single+3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
Platform: |
Size: 1220608 |
Author: 徐文 |
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Description: 基于s5pc100开发板的linux中断服务程序源代码-the linux device source code based s5
pc100 devlopment bozrd。
Platform: |
Size: 1024 |
Author: 混混 |
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