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[VHDL-FPGA-Veriloghgb_pci_host

Description: 内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持: 1、 对目标PCI_T进行配置; 2、 对目标进行单周期读写; 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
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