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Description: PCI Arbitor by VHDL -PCI Arbitor by VHDL
Platform: |
Size: 4096 |
Author: Winsam Tung |
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Description: PCI 仲裁代码/ PCI BUS ARBITER
//WRITTEN BY MARIA GEORGE
`include "c:\pasic\spde\data\macros.v"
module Arbiter (REQ_, reset_, clk_in, frame_, irdy_, GNT_, adbus, cbe)
parameter MASTERS = 6 //This code can handle a maximum of six masters.-pci_arb code
/ PCI BUS ARBITER
//WRITTEN BY MARIA GEORGE
`include "c:\pasic\spde\data\macros.v"
module Arbiter (REQ_, reset_, clk_in, frame_, irdy_, GNT_, adbus, cbe)
parameter MASTERS = 6 //This code can handle a maximum of six masters.
Platform: |
Size: 3072 |
Author: 王军 |
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Description: PCI-9101数据采集,以VB对数字量和模拟量之间的转换，8道数据的采集做了简单的编程，以双极性的方式采集，相对上次（0，10V），这次以（-5V，+5V）转换进行编程采集。希望对做工程控制的朋友有所帮助！ -PCI-9101 data acquisition, in VB and analog to digital conversion between eight data collection program to do a simple, bipolar way to collect, relatively Last (0,10 V), this time to (-5V,+5 V) conversion program acquisition. Want to do engineering controls to help a friend!
Platform: |
Size: 54272 |
Author: moneyofficer |
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Description: This is part of rtl818x pci OpenSource driver - v 0.1.,This is part of rtl818x pci OpenSource driver - v 0.1.
Platform: |
Size: 26624 |
Author: lkow89 |
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Description: This part of rtl818x pci OpenSource driver for Linux.- v 0.1-This is part of rtl818x pci OpenSource driver for Linux.- v 0.1
Platform: |
Size: 26624 |
Author: uonaoujeng |
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Description: 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v”
Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and
write address generation and full, almost full, empty and almost empty status generation.
It also generates read and write allow signals, which are used for enabling/disabling
memory used for FIFO. Control logic can be used for independent read and write clocks.
Platform: |
Size: 1946624 |
Author: chen |
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