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[VHDL-FPGA-Verilog] pi_ctrl

Description: VHDL实现PI调节的算法。内部使用整数计算，避开了浮点数的运算。仿真结果正确-VHDL realize PI regulator algorithm. Internal use integer calculations to avoid the floating point arithmetic. The simulation results correctly
Platform: | Size: 1024 | Author: 刘新 | Hits:

[VHDL-FPGA-Verilog] controller

Description: PI controller and its source code
Platform: | Size: 2048 | Author: sanjivkumar | Hits:

[VHDL-FPGA-Verilog] lock-and-lcd

Description: 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码输入错误时，LED灯D8亮，并在LCD显示屏上显示字符串“NO!!You stupid!!you are worry!!!”其中，LCD显示作为本次设计的核心内容，字符型LCD通常有14条引脚线或16条引脚线的LCD，多出来的2条线是背光电源线VCC(15脚)和地线GND(16脚)，其控制原理与14脚的LCD完全一样-Base YuBo gen experiment box UP- FPGA2C35- Ⅱ and director- Verilog HDL hardware description language, divided into key input module, the LED indicator light module and LCD display module, the BTN1, BTN2 buttons as input the input password and set in four matches, the password by D1, D2 and D3, D4 four lamp that LED lamp to indicate input password of digits. Boot, LCD display "HELLO!!!!!!!!!! The code: backgound Enter when", a password when right, LED lamp, while D7 light displayed on the LCD screen experiment box string "Good!! Well done! You right!!!" hero When a password mistake, LED lamp light, and in D8 displayed on the LCD screen "NO!! You string can be hindered stupid!!!!!!!!!!!!!!!!!" hero Among them, LCD display as the core content of the design, character type LCD usually has 14 pin line or 16 pins line of LCD, extra 2 line is backlit cord VCC (15 feet) and landlines GND (16 feet), the control principle and 14 feet LCD exactly the same
Platform: | Size: 3072 | Author: 吴寿武 | Hits:

[VHDL-FPGA-Verilog] SPI-Verilog-123

Description: spi slave code s pi slave code spi slave code -spi slave code spi slave code spi slave code spi slave code
Platform: | Size: 16384 | Author: 何莉 | Hits:

[VHDL-FPGA-Verilog] filter_signed_and_unsigned

Description: FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
Platform: | Size: 3072 | Author: 范慧敏 | Hits:

[VHDL-FPGA-Verilog] pingjie1

Description: 基于fpga的pi/4dqpsk 调制，用Verilog语言编写(Pi/4dqpsk modulation based on FPGA, written in Verilog language)
Platform: | Size: 3025920 | Author: maerzaizai | Hits:

[VHDL-FPGA-Verilog] PI

Description: PID调节器，非常好用的PID调节器模块(PID regulator, very easy to use PID regulator module)
Platform: | Size: 1819648 | Author: wzy007 | Hits:

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