Search - PIPELINED ADDER

[Other resource] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 809 | Author: qjyong | Hits:

[Other] VLSIASS2

Description: Self timed pipelined adder
Platform: | Size: 978634 | Author: tobyli | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[Other] VLSIASS2

Description: Self timed pipelined adder
Platform: | Size: 977920 | Author: | Hits:

[VHDL-FPGA-Verilog] 8adderverilog

Description: 8位加法器的实现，非流水线结构，很不错。我测试过，效率比较高-8-bit adder realization, non-pipelined structure, is pretty good. I
Platform: | Size: 1024 | Author: 张明 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Platform: | Size: 3072 | Author: chenyi | Hits:

Description: TMS320VC5416的主要特征有： (1)优化的CPU结构：增强的多总线结构，数据总线具有总线保持特性；40bit的算术逻辑单元（ALU），包括两个独立的40bit的累加器，一个40bit的桶形移位器；一个17×17的乘法器连接一个40bit专用加法器，可用来进行非流水线式的单周期乘/累加（MAC）操作等。 -The main features of the TMS320VC5416 are: (1) to optimize the structure of the CPU: Enhanced multi-bus architecture, data bus has a bus to maintain properties 40bit arithmetic logic unit (ALU), including the two independent 40bit accumulator, a Barrel shifter of 40bit a multiplier of 17 × 17 to connect a dedicated 40bit adder that can be used to carry out non-pipelined single-cycle by/accumulate (MAC) operation.
Platform: | Size: 703488 | Author: wshh | Hits:

[VHDL-FPGA-Verilog] leijiaqi

Description: 16位流水线加法累加器，用VHDL语言实现，编译仿真通过。-16-bit pipelined adder accumulator, using VHDL language, compiled simulation through.
Platform: | Size: 221184 | Author: liuxing | Hits:

[VHDL-FPGA-Verilog] adder

Description: 设计一个16×16位的流水线乘法器。乘法器部分采用16×16进位保留（Carry-save）阵列构成。最后一行部分积产生单元要求采用超前进位构成。 -Design of a 16 x 16 pipelined multiplier. Multiplier by 16 x 16 carry save array ( Carry-save ). The last line of the partial product generation unit requires use of carry lookahead.
Platform: | Size: 2048 | Author: raul | Hits:

[VHDL-FPGA-Verilog] Fast-adder-design-using-verilog

Description: 用Verilog设计各种快速加法器（四位先行进位加法器、选择进位加法器、流水线加法器）-Verilog design all kinds of fast adder (four first adder, select adder pipelined adder)
Platform: | Size: 941056 | Author: zhxuqin | Hits:

[VHDL-FPGA-Verilog] code

Description: 32bits流水线加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits pipelined adder verilog language, xilinx chip run through
Platform: | Size: 1024 | Author: 许阳 | Hits:

[VHDL-FPGA-Verilog] Adder

Description: 8bit low power pipelined adder-8bit low power pipelined adder
Platform: | Size: 1024 | Author: arev | Hits:

[ARM-PowerPC-ColdFire-MIPS] 32bit_pipeline_adder

Description: 基于HSPICE的32位流水线加法器设计-HSPICE-based 32-bit pipelined adder design
Platform: | Size: 8318976 | Author: 田小新 | Hits:

[VHDL-FPGA-Verilog] JIAFA_4

Description: 加法器，采用流水线技术设计四级加法器，VHDL实验-Adder, four pipelined adder technical design, VHDL test
Platform: | Size: 117760 | Author: haby | Hits:

[Software Engineering] add48

Description: add48 是6级流水线方式实现加法-add48 are six ways pipelined adder
Platform: | Size: 991232 | Author: 廖小伟 | Hits:

[Software Engineering] 184081165-16-Bit-Wave-Pipelined-Sparse-Tree-RSFQ-

Description: In this system, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2ADP2.1 fabrication process. Compared to the Kogge–Stone adder, our parallel-prefix sparse-tree adder has better energy efficiency with significantly reduced complexity (at the expense of latency) and almost no decrease in operation frequency. The 16-bit adder core (without SFQ-to-dc and dc-to-SFQ converters) has 9941 Josephson junctions occupying an area of 8.5 mm 2. It is designed for the target operation frequency of 30 GHz with the expected latency of 352 ps at the bias voltage of 2.5 mV. The adder chip was fabricated and successfully tested at low frequency for all test patterns with measured bias margins of +9.8 /− 10.7 .
Platform: | Size: 203776 | Author: Fardeen | Hits:

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[Other resource] add_16_pipe

[Other] VLSIASS2

[VHDL-FPGA-Verilog] add_16_pipe

[Other] VLSIASS2

[VHDL-FPGA-Verilog] 8adderverilog

[VHDL-FPGA-Verilog] multiplier

[Other] tms320vc5416

[VHDL-FPGA-Verilog] leijiaqi

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] Fast-adder-design-using-verilog

[VHDL-FPGA-Verilog] code

[VHDL-FPGA-Verilog] Adder

[ARM-PowerPC-ColdFire-MIPS] 32bit_pipeline_adder

[VHDL-FPGA-Verilog] JIAFA_4

[Software Engineering] add48

[Software Engineering] 184081165-16-Bit-Wave-Pipelined-Sparse-Tree-RSFQ-

[VHDL-FPGA-Verilog] Piplined_RCA

[VHDL-FPGA-Verilog] VHDL-Design-of-31-bit-Pipelined-Adder

[Software Engineering] 16位流水线加法器

[Other] 流水线乘法累加器设计

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