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[Other resource] P4_PPC_SDRAM_Reference_Design

Description: SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
Platform: | Size: 33819 | Author: 庞志勇 | Hits:

[Applications] jq_transfile.ARJ

Description: JQ文件传输程序 -JQ file transfer procedure
Platform: | Size: 1228800 | Author: 站长 | Hits:

[Software Engineering] P4_PPC_SDRAM_Reference_Design

Description: SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM-SDRAM reference design: mainly include The following figure shows a high-level block diagram for this reference design followed by a briefdescription of each sub-section. The design consists of: PowerPC processor PLB-OPB bridge BlockRAM Memory Controller SDRAM Controller Two GPIO ports A UART Port External SDRAM
Platform: | Size: 33792 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] vga_geometry_xps92i_s3_v01_00_03

Description: Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.-Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.
Platform: | Size: 3730432 | Author: Praveen | Hits:

[Other] plbv46_slave_burst

Description: PLB for EDK platform datasheet
Platform: | Size: 413696 | Author: alphans | Hits:

[Software Engineering] plb

Description: 图书管理系统可行性分析报告书 软件工程课程设计-Library management system software engineering feasibility analysis report on curriculum design
Platform: | Size: 373760 | Author: 小猪 | Hits:

[VHDL-FPGA-Verilog] I2C_Slave

Description: 这是iic Slave模式的源代码，可用于嵌入式FPGA，挂载在PLB总线上-This is iic Slave mode, the source code for embedded FPGA, mounted on the PLB bus
Platform: | Size: 8192 | Author: 吴言 | Hits:

[VHDL-FPGA-Verilog] fle_lcd_plb

Description: lcd interface using plb bus
Platform: | Size: 208896 | Author: sukan1 | Hits:

[VHDL-FPGA-Verilog] PLB_MG

Description: PLB Macrogate in VHDL
Platform: | Size: 1024 | Author: Prashanth | Hits:

[VHDL-FPGA-Verilog] xapp941

Description: Reference System: PLB Tri-Mode Ethernet MAC
Platform: | Size: 3904512 | Author: fangming | Hits:

[VHDL-FPGA-Verilog] 05_UART_demo

Description: 该UART实例是很简单的EDK工程，在PLB总线上挂载了XPS-uartlite外围设备，作为串口的控制器，一般的EDK工程会将该IP作为基本外围设备来使用。包含bit流文件(在EDK上下载到FPGA上使用），和说明文档。-The UART instance EDK project is very simple and is mounted on the PLB bus the XPS-uartlite peripherals, general EDK works as a serial controller, the IP to use as a basic peripherals. Contains bit stream file downloaded to the FPGA (EDK on use), and documentation.
Platform: | Size: 908288 | Author: dujinzhe | Hits:

[MPI] uart_plb_latest.tar

Description: Uart 功能支持PLB总线，异步收发功能等-Uart desciption
Platform: | Size: 145408 | Author: 南宁 | Hits:

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