Search - PLD VHDL

[Other resource] VHDL

Description: 注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
Platform: | Size: 43546 | Author: 朱明 | Hits:

[Embeded-SCM Develop] EDA技术与PLD设计

Description: 难得一见的"EDA技术与PLD设计"课程的课件--A good lesson on "EDA technique and PLD design".
Platform: | Size: 5948416 | Author: 王斌 | Hits:

Description: 44个vhdl实例注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I/O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-Verilog] fifo_01

Description: 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] BoothMultiplier

Description: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
Platform: | Size: 2048 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] wave_gen

Description: 波形发生器，带TESTBENCH，多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[Embeded-SCM Develop] vhdl

Description:
Platform: | Size: 3072 | Author: math | Hits:

[Post-TeleCom sofeware systems] rs-code

Description: 基于PLD的RS码编译码器设计，用VHDL语言编写，编译通过，测试结果正确。-PLD-based encoding and decoding of RS code design, using VHDL language, the compiler is passed, the test results correctly.
Platform: | Size: 15360 | Author: li.j | Hits:

[Communication] 4cheng4jianpanxianshi

Description: 4乘4键盘识别与显示程序和说明（vhdl）设计了一个的4x4键盘识别与显示模块。小键盘中有0~f共16个按键，小键盘和数码管都连接到PLD芯片上。-4 x 4 keyboard and display identification and description of procedures (vhdl) designed a recognition of the 4x4 keypad and display module. Small keyboard in the 0 ~ f total of 16 keys, small keyboard and digital tube are connected to the PLD chip.
Platform: | Size: 88064 | Author: coolrainy | Hits:

[VHDL-FPGA-Verilog] led

Description: vhdl实现“PLD电子技术”（文字显示）-VHDL achieve PLD electronic technology (text)
Platform: | Size: 1024 | Author: 阿乔 | Hits:

[SCM] VHDL

Description: 注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化 -Note 1: contains a comprehensive statement can not, please amend Note 2: Some PLD only permit I/O port of external tri-state, does not support internal tri-state, the use of when we should pay attention Note 3: the design of RAM
Platform: | Size: 44032 | Author: 朱明 | Hits:

[Embeded-SCM Develop] AAS

Description: PLD设计的定时抢答器报告，有电路原理图，做硬件的朋友可以看看，EPROM7128S的-Answer PLD timing device design report, there are circuit schematics, so a friend can look at hardware, EPROM7128S the
Platform: | Size: 487424 | Author: 麦佳 | Hits:

[Embeded-SCM Develop] FPGA_CPLD

Description: 该PDF文档是CPLD/FPGA的入门教程。里面叙述了PLD的基本结构，选择CPLD/FPGA的方式方法。-The PDF document is the CPLD/FPGA introductory tutorial. Which describes the basic structure of PLD, select the CPLD/FPGA ways.
Platform: | Size: 192512 | Author: 李鑫旺 | Hits:

[Other] switch

Description: 四个拨码开关，拨上去对应的前四个LED灯亮，体现了pld io功能的灵活。请把拨码开关右上方的跳线帽跳上，同时拔掉ADC0804的跳线帽。-Four DIP switches, dial up the corresponding first four LED lights, reflect the function of flexible pld io. Please dial code switch at the top right of the jumper cap jumped, and pulled out the jumper cap ADC0804.
Platform: | Size: 64512 | Author: liupeinan | Hits:

[Embeded-SCM Develop] PLD

Description: 10分钟学会PLD,仿真，下载，原理图，布线-10 minutes Society PLD, simulation, download, schematics, wiring
Platform: | Size: 1186816 | Author: 黄磊 | Hits:

[Books] logicdesigforFPGA

Description: 高级FPGA教学实验指导书－逻辑设计部分.pdf QuatusII5.0 是Altera 公司的最新产品。MaxplusII 是一套非常成功的PLD 开发软件，虽然QuartusII 已经推出了4 年，并且Altera 宣布不再对MaxplusII 进行升级，但至今仍有非常多的工程师在使用MaxplusII。 Altera 在QuartusII 中允许将软件界面设置为 MaxplusII 风格，以吸引MaxplusII 的用户转向QuartusII。安装QuartusII 时，软件会自动询问，你准备使用何种界面：QuartusII 还是Maxplus-Senior FPGA experimental teaching guide book- part of logic design. PdfQuatusII5.0 are Altera
Platform: | Size: 1091584 | Author: 董军 | Hits:

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