Description: This project allows you to learn communication systems in greater depth. It contains the Simulink files (*.mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation.
The idea here is to implement experiments of a traditional communication lab using Simulink.
Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories-This project allows you to learn communication systems in greater depth. It contains the Simulink files (*. mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation. The idea here is to implement experiments of a traditional communication lab using Simulink.Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories Platform: |
Size: 2468864 |
Author:haibak |
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Description: C语言实现了数字锁相环的程序，不过程序比较复杂，得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model Platform: |
Size: 24576 |
Author:蔡科 |
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Description: gps信号的跟踪，采用锁相环实现，包括码环的跟踪和载波的跟踪环-gps signal tracking, the use of PLL implementation, including code and carrier tracking loop tracking loop Platform: |
Size: 2048 |
Author:lucy |
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Description: 这是一个Matlab实现的三逆变器的Simulink仿真。电流环反馈，pll环控制相位无偏差。-This is a Matlab implementation of the three inverter Simulink simulation. Current loop feedback, pll loop control phase without bias. Platform: |
Size: 8192 |
Author:张妍 |
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Description: 1、资料包含二阶环路设计简要说明，Matlab程序，Matlab程序模拟FPGA工作方式，对各变量进行了量化处理
2、资料包含使用Vivado2015.4.2版本的工程文件，可直接运行查看仿真结果
3、参考资料为杜勇老师的《锁相环技术原理及其FPGA实现》(1. The data include a brief description of the second-order loop design. The MATLAB program and the MATLAB program simulate the working mode of the FPGA and quantify the variables.
2, the data contains Vivado2015.4.2 version of the engineering document, which can be run directly to see the simulation results.
3. Reference material is Du Yong's PLL technology principle and FPGA implementation.) Platform: |
Size: 32550912 |
Author:三百钱 |
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Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.) Platform: |
Size: 10222592 |
Author:丶大娱乐家 |
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Search - PLL matlab implementation