Search - PLL vhdl

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[VHDL-FPGA-Verilog] pll DL : 1: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Update : 2025-02-17 Size : 109kb Publisher : 孙犁
[VHDL-FPGA-Verilog] 数字锁相环设计源程序 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Update : 2025-02-17 Size : 118kb Publisher : 杰轩
[VHDL-FPGA-Verilog] fdpll DL : 0: 简单的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的滤波有很好的效果，而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Update : 2025-02-17 Size : 2kb Publisher : 陈德炜
[VHDL-FPGA-Verilog] Div20PLL DL : 0: 使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
Update : 2025-02-17 Size : 1kb Publisher :
[Software Engineering] VHDL_PLL DL : 0: 介绍了锁相环PLL的实现原理，可以为VHDL实现PLL提供参考。-introduced PLL PLL The principle for VHDL PLL reference.
Update : 2025-02-17 Size : 94kb Publisher : CGT
[VHDL-FPGA-Verilog] pll1218 DL : 0: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Update : 2025-02-17 Size : 106kb Publisher : sss
[Communication-Mobile] my_pll DL : 0: VHDL程序，使用锁相法实现位同步的算法，并可以对算法进行仿真-VHDL, the use of lock-in-law to achieve the synchronization algorithm, the algorithm can be simulated
Update : 2025-02-17 Size : 1kb Publisher : 笑容
[Communication-Mobile] EXPT12_10_PHAS_PLL1 DL : 0: VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码-VHDL shifter DDS signal generator design code. Directly extract can run on open .. write their own code
Update : 2025-02-17 Size : 117kb Publisher : haiou
[VHDL-FPGA-Verilog] pll DL : 0: fpga中pll时钟实现的源代码，可实现倍频或分频-pll clock in the FPGA to achieve the source code, can be realized or sub-octave frequency
Update : 2025-02-17 Size : 3kb Publisher : 张恒
[Post-TeleCom sofeware systems] Phase_Locked_Loop DL : 0: 对一般的PLL及APLL,定点PLL进行了MATLAB SIMULINK仿真，可以由程序直接生成PLL的VHDL和C源代码-General PLL and APLL, fixed-point MATLAB SIMULINK a PLL simulation, can be directly generated by the PLL of VHDL and C source code
Update : 2025-02-17 Size : 389kb Publisher : joshua
[VHDL-FPGA-Verilog] PLL DL : 0: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Update : 2025-02-17 Size : 788kb Publisher : 许东滨
[VHDL-FPGA-Verilog] pll DL : 0: 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
Update : 2025-02-17 Size : 174kb Publisher : 冯勇
[matlab] FractionalPLLDesign DL : 0: 是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code-Is about the design of sigma delta PLL detailed papers, papers in the specific design details, and in the appendix corresponding matlab, vhdl code
Update : 2025-02-17 Size : 3.63mb Publisher : xin
[VHDL-FPGA-Verilog] pll DL : 0: 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
Update : 2025-02-17 Size : 9.61mb Publisher : gk
[VHDL-FPGA-Verilog] PLL DL : 0: verilog PLL的代码，和PLL 的功能介绍，希望能通过，只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
Update : 2025-02-17 Size : 18kb Publisher : gjj
[Communication-Mobile] pll DL : 0: 一个实现任意倍频的，输入参考频率未知的pll，已综合实现-frequency multiple rely on dpll，unknown reference input clock
Update : 2025-02-17 Size : 4kb Publisher : 刘彻
[VHDL-FPGA-Verilog] PLL DL : 0: 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
Update : 2025-02-17 Size : 21kb Publisher : 水淼
[Other] pll DL : 0: 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loop method, and use complex programmable logic device CPLD to be achieved, given the main modules of the system design process and simulation results .
Update : 2025-02-17 Size : 206kb Publisher : lilei
[VHDL-FPGA-Verilog] AD-PLL DL : 0: 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
Update : 2025-02-17 Size : 2kb Publisher : yzn8625
[VHDL-FPGA-Verilog] PLL.ZIP DL : 0: the code specifies how to model a pll using vhdl code
Update : 2025-02-17 Size : 6kb Publisher : mridula

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