Search - Pal vhdl

[Other resource] scaler

Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。
Platform: | Size: 9734 | Author: wgy | Hits:

[VHDL-FPGA-Verilog] VGA_verilogHDL_VHDLcode

Description: VGA verilogHDL /VHDL 实现-VGA verilogHDL/VHDL to achieve
Platform: | Size: 131072 | Author: lin | Hits:

Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Platform: | Size: 9216 | Author: wgy | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[VHDL-FPGA-Verilog] 06-50

Description: PAL decoder, spartan 3 FPGA
Platform: | Size: 171008 | Author: ass | Hits:

[Graph program] TFT2VGA

Description: 可以从TFT 转vga-TFT TO vga !!!!!!!!!!!
Platform: | Size: 280576 | Author: yezi | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_TV_PAL

Description: DE2上的基于FPGA视频开发资料第3部分-DE2 video
Platform: | Size: 269312 | Author: 刘志文 | Hits:

[Other] PAL_VEDIOSIGNAL

Description: 基于VHDL 的PAL视频图像格式-VHDL
Platform: | Size: 2048 | Author: 任乐 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram configuration module can be directly useful
Platform: | Size: 79872 | Author: 熊文 | Hits:

[VHDL-FPGA-Verilog] CVBS

Description: CVBS，用于生成模拟视频信号，NTSC/PAL可选-CVBS Signal Generator，NTSC/PAL could be selected
Platform: | Size: 7168 | Author: 张欣 | Hits:

[VHDL-FPGA-Verilog] VIDEOGEN_PAL

Description: Spartan-3AN based PAL video sync generator
Platform: | Size: 1024 | Author: t404383 | Hits:

[VHDL-FPGA-Verilog] vga_focus_code

Description: 用VHDL编写的PAL转换为VGA格式的源代码，同时包括摄像头的自动变焦控制源码-PAL prepared using VHDL VGA format is converted to the source code, including the automatic zoom camera control source
Platform: | Size: 139264 | Author: | Hits:

[VHDL-FPGA-Verilog] vhdl_pal.tar

Description: VHDL PAL video generating "library" and test usage
Platform: | Size: 98304 | Author: zz_indigo | Hits:

[VHDL-FPGA-Verilog] PAL

Description: PAL_D电视信号VHDL以及verilog源程序！ FPGA设计PAL_D电视信号！VHDL源程序！两个程序都是黑白的video信号，输出可以直接在视频显示器上显示。 -PAL_D TV signal VHDL and Verilog source!
Platform: | Size: 12288 | Author: zq | Hits:

[Other] VHDL-VERILOG_HDL

Description: 基于FPGA的视频图像采集系统的设计与实现的ＣＣＤ图像传感器采集图像，经ＤＳＰ处理后输出的ＰＡＬ制数字视频信-FPGA based video image acquisition system design and implementation of the CCD image sensor sensor image acquisition, after the treatment by DSP output PAL for digital video.
Platform: | Size: 12288 | Author: 演的 | Hits:

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