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[Other Embeded program] NIOS_HOST_MOUSE_VGA

Description: Nios系统, 加入了VGA控制器和USB鼠标控制器-Nios system, add a VGA controller and the USB mouse controller
Platform: | Size: 909312 | Author: | Hits:

[Books] Quartus-guide

Description: quartus的教程，是初学者使用FPGA的好老师，介绍了quartus的使用方法，并且有例子-quartus curricula, the use of FPGA beginners is a good teacher. quartus introduced the use, and is an example
Platform: | Size: 1183744 | Author: mh | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[Post-TeleCom sofeware systems] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。-Altera
Platform: | Size: 1355776 | Author: YangJun | Hits:

[VHDL-FPGA-Verilog] PS_2

Description: 此模块用于"PS/2接口的鼠标或键盘"与"具有外部读写的8位并口单片机"双向通信模块. Verilog HDL语言编写,在Quartus II 8.1 (32-Bit)软件中编译,并下载至EPM7128SLC84-10芯片中通过. 文件中有详细的注解. 此模块具有对于PS/2时钟和数据线的滤波功能,这样减少外部干扰，保证通信的可靠性！ -This module for the "PS/2 mouse or keyboard interface" and "read and write with an external parallel port single-chip 8" two-way communication module. Verilog HDL language, in the Quartus II 8.1 (32-Bit) software compiler and downloaded to EPM7128SLC84-10 chip through. document detailed comments. This module has the PS/2 clock and data line filtering, so that to reduce the external interference, and ensure the reliability of communication!
Platform: | Size: 5120 | Author: yuantielei | Hits:

[VHDL-FPGA-Verilog] BaseGate

Description: ep2c5 实现 逻辑门 verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation
Platform: | Size: 320512 | Author: lizhuodong | Hits:

[VHDL-FPGA-Verilog] Timer

Description: ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
Platform: | Size: 497664 | Author: lizhuodong | Hits:

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio(Modified)

Description: 在DE2开发板上实现的SD卡mp3音乐播放器。硬件部分用Verilog语言编写，在Quartus上编译；软件部分用C语言编写，在Nios2上编译运行。-DE2 development board in the realization of the SD card mp3 music player. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2.
Platform: | Size: 3018752 | Author: 符玉襄 | Hits:

[VHDL-FPGA-Verilog] DE2_NIOS_HOST_MOUSE_VGA

Description: 在DE2开发板上实现的VGA输出游戏。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。把DE2板和显示器键盘连起来即可使用。-Development in the DE2 board game to achieve the VGA output. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2. The DE2 board and display can be used to connect the keyboard.
Platform: | Size: 1627136 | Author: 符玉襄 | Hits:

[VHDL-FPGA-Verilog] DE2_NET

Description: 用DE2开发板实现的网络控制器。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。程序已经过测试，功能完好。-DE2 development board with the realization of the network controller. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2. Procedure has been tested, function well.
Platform: | Size: 1601536 | Author: 符玉襄 | Hits:

[VHDL-FPGA-Verilog] hgfdg

Description: Quartus? II 相关的语言 详细介绍了VHDL verilog软件开发过程-Quartus ? II related language detailed introduces the verilog VHDL software development process
Platform: | Size: 12838912 | Author: 王子 | Hits:

[Other] dds

Description: 一个用verilog编写的dds发生器，希望能对大家有所帮助 -A set of relatively good the quartus learning Chinese information for beginners, more practical, oh. .
Platform: | Size: 692224 | Author: 李妮 | Hits:

[Other Riddle games] pingpangqiu

Description: 本文使用 FPGA 芯片来模拟实际的乒乓球游戏。本设计是基于 Altera 公司的 FPGA Cyclone II 芯片 EP2C5T144C8 的基础上实现，运用 Verilog HDL 语言编程，在 Quartus II 软件上进行编译、仿真，最终在开发板上成功实现下载和调试。 -This article uses the FPGA chip to simulate the actual game of table tennis. The design is based Altera FPGA Cyclone II the chip EP2C5T144C8 the company based on the use of Verilog HDL language programming, compiled in the Quartus II software, simulation, and ultimately successful download and debug on the development board.
Platform: | Size: 49152 | Author: jingdizhimo | Hits:

[VHDL-FPGA-Verilog] parall_ad_da

Description: Verilog初学者实验程序。已在quartus下测试成功。-Verilog beginners experimental procedures. Been in quartus under test success.
Platform: | Size: 902144 | Author: chirs | Hits:

[VHDL-FPGA-Verilog] serial_adda

Description: 串行AD/DA的实验。Verilog初学者实验程序。已在quartus下测试成功。-Serial AD/DA experiments. Verilog beginners experimental procedures. Been in quartus under test success.
Platform: | Size: 806912 | Author: chirs | Hits:

[VHDL-FPGA-Verilog] 13_flash

Description: 用于读写8位数据口的FLASH芯片，使用Quartus II开发，Verilog文件-used to read or write the 8bit Flash Chip,developed by Quartus with Verilog language
Platform: | Size: 1024 | Author: 苏羽金 | Hits:

[Software Engineering] EJEMPLOS-(1)

Description: quartus ii introduction to verilog
Platform: | Size: 82944 | Author: lucero | Hits:

[VHDL-FPGA-Verilog] dm9000a_init

Description: 在QUARTUS开发环境下的，verilog实现dm9000a的初始化-In QUARTUS development environment, verilog realize dm9000a initialization
Platform: | Size: 2804736 | Author: 孟晗 | Hits:

[VHDL-FPGA-Verilog] nios_ruanhe_spi_3

Description: 这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。-This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact
Platform: | Size: 29037568 | Author: 高政 | Hits:

[VHDL-FPGA-Verilog] eluosi_game

Description: 使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language
Platform: | Size: 2177024 | Author: 韩闯 | Hits:
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