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[Other resource] 66_FIR

Description: 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
Platform: | Size: 8452 | Author: 佴立峰 | Hits:

[Other resource] 02-Designing_with_Quartus_II_v5_0

Description: 使用Quartus II 5.0开发指导手册-use Quartus II 5.0 development guidance manual
Platform: | Size: 11830476 | Author: KC_P | Hits:

[Special Effects] videofram

Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: | Size: 1325 | Author: 陈刚峰 | Hits:

[Other resource] chap3

Description: adder4 hdl ok in Quartus II 5.1
Platform: | Size: 4291 | Author: emic | Hits:

[Compress-Decompress algrithms] cmi

Description: cmi encoder and decoder ok in Quartus ii 5.1
Platform: | Size: 214994 | Author: emic | Hits:

[Embeded-SCM Develop] CF_NiosII5.0

Description: Compact Flash Support For Nios II 5.0, To download supporting materials for this new Compact Flash support, download the following .zip file, extract to a computer with Quartus II 5.0 & Nios II 5.0 installed, and proceed to use the hardware and/or software examples of your choice to proceed. Additional information is available in the readme.txt document, included in the top-level of the .zip file
Platform: | Size: 1589301 | Author: Robert | Hits:

[OS Develop] deccount2.5

Description: altera Quartus II 減法器使用 配合LED，可自動與手動按鈕控製。 (含電路)
Platform: | Size: 40423 | Author: 陳小龍 | Hits:

[Software Engineering] mycpu

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。
Platform: | Size: 800692 | Author: 陈佳 | Hits:

[Other resource] czcjjq

Description: 使用Quartus II设计并制作一台出租车计价器不同情况具有不同的收费标准行驶公里： 在行车三千米以内时，按起步价10元收费，超过3千米部分，以每千米1.6元计算。 l 途中等待（>2min 开始收费） 在等待时间小于2分钟以内时不收取额外费用，大于2分钟，按每分钟1.5元计算。
Platform: | Size: 69262 | Author: yingzhua | Hits:

[Other resource] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的
Platform: | Size: 475864 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] 66_FIR

Description: 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
Platform: | Size: 8192 | Author: 佴立峰 | Hits:

[Other] 02-Designing_with_Quartus_II_v5_0

Description: 使用Quartus II 5.0开发指导手册-use Quartus II 5.0 development guidance manual
Platform: | Size: 11830272 | Author: KC_P | Hits:

[Special Effects] videofram

Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: | Size: 1024 | Author: 陈刚峰 | Hits:

[Embeded-SCM Develop] CF_NiosII5.0

Description: Compact Flash Support For Nios II 5.0, To download supporting materials for this new Compact Flash support, download the following .zip file, extract to a computer with Quartus II 5.0 & Nios II 5.0 installed, and proceed to use the hardware and/or software examples of your choice to proceed. Additional information is available in the readme.txt document, included in the top-level of the .zip file
Platform: | Size: 1589248 | Author: Robert | Hits:

[Software Engineering] mycpu

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, such as decoding circuitry. Simulated clock pulse is also given. Has been run through the Quartus II 5.0. Can be addressed to the need to design bus architecture students CPU reference point.
Platform: | Size: 800768 | Author: 陈佳 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[Other] DSP_yingyongjishu

Description: 现代DSP技术 是西安电子科技大学的课件！有fft，fir，dspbulder，iir，quartus II 等内容，非常的详细，值得一看的好的ppt啊。我把好的资料贡献给大家看看啊1-Modern DSP technology is the Xi' an University of Electronic Science and Technology Courseware! There fft, fir, dspbulder, iir, quartus II and so on, very detailed, good to see ah ppt. Contribution to the information I give you a good look at ah 1
Platform: | Size: 25252864 | Author: 卢超 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 教你在Quartus II中如何实用LPM库，对与FPGA系统设计有很好指导作用-Teach you how to Quartus II in the LPM utility library, with the FPGA system design have a very good guide
Platform: | Size: 352256 | Author: 钟桂东 | Hits:

[VHDL-FPGA-Verilog] Quartus

Description:
Platform: | Size: 4136960 | Author: zhongguangxi | Hits:

[Other] Quartus-II使用教程---图形输入

Description: Quartus-II使用教程---图形输入(Quartus-II tutorial -- Graphical Input)
Platform: | Size: 1443840 | Author: 阿联联联 | Hits:
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