Search - QuartusII 8.1

[Other] 8.1

Description: ALTERA quartusii 破解 -quartusii
Platform: | Size: 93184 | Author: 都想风 | Hits:

[VHDL-FPGA-Verilog] vga_colors

Description: 该项目在VGA显示器上显示8色竖彩条。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on the monitor VGA color vertical color 8. VerilogHDL language used in Altera' s development environment QuartusII verification through.
Platform: | Size: 15360 | Author: submars | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
Platform: | Size: 4096 | Author: 邵捷 | Hits:

[VHDL-FPGA-Verilog] 16qam——modulation

Description: verilog编写的16qam调制程序，将所有东西装入工程，运行mmm16主程序。其中载波为一个周期采十个点，并乘以2^8-1取整数。在quartusII运行通过。-verilog modulation procedures 16qam prepared all things into works mmm16 to run the main program. One carrier for a cycle of 10 points taken, and multiplied by an integer from 2 ^ 8-1. Running through the quartusII.
Platform: | Size: 5120 | Author: 王力宏 | Hits:

[VHDL-FPGA-Verilog] vga_colors

Description: 在VGA显示器上显示8色竖彩条,使用verilog语言编写，quartusII编译成功-VGA monitor display in 8-color vertical color
Platform: | Size: 15360 | Author: Doolittle | Hits:

[VHDL-FPGA-Verilog] VGA_test50m

Description: 本代码功能为实现VGA显示功能，即实现在显示器上显示640*480彩条。程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve the VGA display, that is, to achieve the display 640* 480 Color display. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 47104 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] IR

Description: 本代码功能为实现38/30KHZ红外线接收功能程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve 38/30KHZ infrared reception procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 78848 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] ps2test

Description: 本代码功能为实现接收PS2键盘编码功能。程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve the receiver PS2 keyboard encoding. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 118784 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] recuart_50m

Description: 本代码功能为实现接收PC发送的串口数据功能程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions to achieve the receiving PC to send serial data capabilities procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 48128 | Author: huangbin | Hits:

[VHDL-FPGA-Verilog] halfclk

Description: 本代码功能为实现输入时钟的1.5分频功能。程序通过quartusII 8.1编译，使用verilog语言编写。可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。（开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm）有需要的朋友可以下载参考-The code functions as the input clock frequency of 1.5 features. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 28672 | Author: huangbin | Hits:

[VHDL-FPGA-Verilog] FPGAdds

Description: 用verilog写的DDS程序，请用QuartusII 8.1以上版本打开-DDS program written using verilog, please QuartusII 8.1 or later to open
Platform: | Size: 1613824 | Author: 吴恒 | Hits:

[VHDL-FPGA-Verilog] conformPulse

Description: 本程序实现了对两相混合式电机提供4路驱动信号，相位相差90，180，另外也提供了拨码开关控制的频率输出选择，输出频率最大是5M,外部全局时钟是10M，采用的芯片是epm7128slc-84-15, 管脚分配可以参考管脚分配文件，对应驱动电机信号是两相双极性A+,A-,B+,B-. 编译环境是quartusII 8.0,这段代码可用来调试步进电机双桥驱动电路，也可用当信号发生器使用。-The program realization of two-phase hybrid motor provides 4-way drive signal, the phase difference of 90,180, also provided additional DIP switch control the frequency output options, the maximum output frequency is 5M, the external global clock is 10M, use the chips is epm7128slc-84-15, pin distribution can refer to the pin allocation file, the corresponding drive motor is a two-phase bipolar signal A+, A-, B+, B-. build environment is quartusII 8.0, this code can be used to debug step into the electrical double bridge driver circuit, can also be used when the signal generator.
Platform: | Size: 27648 | Author: lijunke | Hits:

[VHDL-FPGA-Verilog] 3-8-encoder-design

Description: 　通过应用QUARTUSII开发软件对3—8译码器进行设计，给出运行程序和结果-Development through the application of QUARTUSII 3-8 decoder software for design, operational procedures and results are given
Platform: | Size: 19456 | Author: renee | Hits:

[VHDL-FPGA-Verilog] FIR_IP_lowpass

Description: 8阶FIR_IP的VHDL代码以及QuartusII的顶层文件-FIR_IP the VHDL code of order 8 and the top-level file QuartusII
Platform: | Size: 7205888 | Author: 李龙 | Hits:

[Technology Management] QuartusII-8.0

Description: QuartusII的安装与破解方法详解，如何安装QIuartusII及IDE软件，并附带破解方法-QuartusII installation and crack method Detailed how to install QIuartusII and IDE software and comes with crack
Platform: | Size: 7161856 | Author: 张晓瑞 | Hits:

[VHDL-FPGA-Verilog] CODER

Description: 基于FPGA的8线-3线优先编码器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA eight line-3 line is preferred encoder design, QuartusII compile, USES the VHDL language.
Platform: | Size: 226304 | Author: 左云华 | Hits:

[VHDL-FPGA-Verilog] fft_8

Description: 基于quartusiI的8位傅立叶变换。verlog程序加仿真。-Based quartusiI eight Fourier transform. verlog program plus simulation.
Platform: | Size: 22291456 | Author: 一棵树 | Hits:

[VHDL-FPGA-Verilog] pcf8563

Description: pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示-pcf8563, written in quartusII VERILOG digital clock program, eight digital display
Platform: | Size: 1040384 | Author: yyq | Hits:

[VHDL-FPGA-Verilog] Graphic-design-

Description: 基于QUARTUSII图形输入电路的设计 1、通过一个简单的3—8译码器的设计,掌握组合逻辑电路的设计方法。 2、初步了解QUARTUSII原理图输入设计的全过程。 3、掌握组合逻辑电路的静态测试方法。 -Graphic design QUARTUS II based on the input circuit
Platform: | Size: 564224 | Author: 漆广文 | Hits:

[VHDL-FPGA-Verilog] VGA_pic_200x200x3(ok)

Description: altera 系列FPGA实现的VGA显示8色的图片，调试通过，开发环境quartusii , 语言verilog。-Altera series FPGA to achieve the VGA display 8 color images, debugging through, the development environment QuartusII, language verilog.
Platform: | Size: 6878208 | Author: PrudentMe | Hits:

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[Other] 8.1

[VHDL-FPGA-Verilog] vga_colors

[VHDL-FPGA-Verilog] FIFO

[VHDL-FPGA-Verilog] 16qam——modulation

[VHDL-FPGA-Verilog] vga_colors

[VHDL-FPGA-Verilog] VGA_test50m

[VHDL-FPGA-Verilog] IR

[VHDL-FPGA-Verilog] ps2test

[VHDL-FPGA-Verilog] recuart_50m

[VHDL-FPGA-Verilog] halfclk

[VHDL-FPGA-Verilog] FPGAdds

[VHDL-FPGA-Verilog] conformPulse

[VHDL-FPGA-Verilog] 3-8-encoder-design

[VHDL-FPGA-Verilog] FIR_IP_lowpass

[Technology Management] QuartusII-8.0

[VHDL-FPGA-Verilog] CODER

[VHDL-FPGA-Verilog] fft_8

[VHDL-FPGA-Verilog] pcf8563

[VHDL-FPGA-Verilog] Graphic-design-

[VHDL-FPGA-Verilog] VGA_pic_200x200x3(ok)

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