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[Other resource] vga.niosII.compent.v

Description: 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
Platform: | Size: 6599 | Author: Ray ZH | Hits:

[Other resource] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明
Platform: | Size: 62930 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] sram+lcd

Description: 用vhdl格式写的sram源代码，把扩展名txt改为.v即可-VHDL format used to write the SRAM source code, to be re-txt extension. V can
Platform: | Size: 2048 | Author: 郭艳红 | Hits:

[OS Develop] FIFO

Description: fifo.v verilog实现的先进先出存储器-fifo.vverilog realize the FIFO memory
Platform: | Size: 2048 | Author: patrick | Hits:

[VHDL-FPGA-Verilog] doubleportram

Description: 高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform
Platform: | Size: 303104 | Author: liujingxing | Hits:

[VHDL-FPGA-Verilog] wave_produce_VHDL

Description: --文件名：mine4.vhd。 --功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节量阶为1/51V）。 --其中方波的幅度还可通过u0、d0调节输出数据的归一化幅值（AMP0）进行进一步 --细调（调节量阶为1/（51*255）V）。方波A的占空比通过zu、zp按键调节（调节 --量阶1/64*T）。系统采用内部存储器——RAM实现任意输入波形的存储，程序只支 --持键盘式波形特征参数置入存储，posting 为进入任意波置入(set)、清除（clr）状态 --控制信号，SSS控制存储波形的输出。P180为预留端口， -err
Platform: | Size: 10240 | Author: huangsong | Hits:

[VHDL-FPGA-Verilog] vga_hex_disp

Description: 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera.
Platform: | Size: 18432 | Author: submars | Hits:

[Other] MN101EF51_52A-10May09

Description: 松下8Bit单片机 Flash:32K RAM:1K 电压:1.8-5.5V-Panasonic 8Bit Single Chip Flash: 32K RAM: 1K voltage :1.8-5 .5 V
Platform: | Size: 2700288 | Author: 万祥兵 | Hits:

[Windows Develop] TP3115270

Description: 本光盘包含《组态软件设计与开发》一书的所有源程序代码，与书一起配 套使用。运行本光盘的执行程序需要安装Visual C++6.0。 运行第五章的执行程序TcpClient.exe、XEchoServer.exe需要注册Ocx控件 XSockClient.ocx、XSockServer.ocx。 运行第八章的执行程序需要建立ODBC数据源Rms2000，对应的数据库文件为 DB子目录Rms2000.mdb。 系统要求： Pentium 166以上计算机 中文Windows98Se/NT4.0/2000/Me/Xp 32M以上内存 50M以上硬盘剩余空间 开发制作： 王亚民等 出版发行： 西安交通大学出版社 西安电子科技大学出版社-This CD contains " Configuration Software Design and Development," a book of all source code, along with supporting the use of the book. The implementation of programs to run this CD-ROM will need to install Visual C++6.0. Chapter V of the implementation of the program is running TcpClient.exe, XEchoServer.exe need to register Ocx control XSockClient.ocx, XSockServer.ocx. Chapter VIII of the implementation of the program to run need to create ODBC data source Rms2000, the corresponding database file for the DB subdirectory Rms2000.mdb. System requirements: Pentium 166 or more computers in Chinese Windows98Se/NT4.0/2000/Me/Xp 32M RAM 50M over and above the remaining hard disk space development production: Wang Yamin, etc. Published by: Xi' an Jiaotong University Press, Xi' an University of Electronic Science and Technology Publishing House
Platform: | Size: 3714048 | Author: purple | Hits:

[SCM] 8155

Description: 8155是作为输入输出以及RAM扩充的IC.特性如下： 256字节的RAM。一组可编程6位IO口。两组可编程8位IO口。可编程14位二进制计时计数器。 多工地址和数据总线。内部地址锁存。8155采用40脚双列直插封装，单一＋5v电源。-8155 as input and output, and RAM expansion of IC. Features: 256 bytes of RAM. A programmable six IO port. Two programmable 8-bit IO port. 14-bit binary counter programmable timer. Multiplexing address and data bus. Internal address latch. 8155 in a 40-foot two-line package, single+5 v power.
Platform: | Size: 173056 | Author: liuxiao | Hits:

[DSP program] DS12887

Description: DS12CR887实时时钟芯片功能丰富，其正常工作电压为3.3 V，工作电压范围为2.97 V～3.63 V，是应用在DSP硬件电路中的理想时钟芯片。DSl2CR887的具体的特性如下： (1) 具有10字节RAM用来存储时间信息。能够自动产生年、月、日、时、分、秒、星期等时间信息，并且有时、分、秒的闹铃功能，温度25℃时每个月的时间误差在±1分钟以内。 (2) 内部自带电池，外部掉电时，温度25℃时其内部时间信息能够保持5年之久。 (3) 对于一天内的时间记录，有12小时制和24小时制两种模式。在12小时制模式中，用AM和PM区分上午和下午。 (4) 时间有二进制数和BCD码两种表示方法。 (5) 内置128字节RAM，其中10字节RAM用来存储时间信息，4字节RAM用来存储控制信息，称为控制寄存器，114字节的通用RAM可供用户使用。 (6) 用户还可对DS12C887进行编程 -DS12CR887 real-time clock chips, and the normal function of rich working voltage is 3.3 V, working voltage range as 2.97 V- a 3.63 V, is used in digital signal processor (DSP) hardware circuit of the ideal clock chip. The specific characteristics of DSl2CR887 are as follows: (1) is used to store the RAM 10 bytes. Automatically generate year, month, day, week, minutes and seconds, such time information, and sometimes, minutes and seconds of alarm functions, while 25 degrees Celsius temperature per month during the time error within ± 1 minute. (2) internal cabin batteries, external power, the internal temperature of 25 degrees Celsius can keep time information for 5 years. (3) for the time of day, 12 hours and 24 hours of two kinds of patterns. In 12 hours system model, AM and PM distinction in the morning and afternoon. (4) time is binary number and BCD two methods. Built-in 128 bytes (5), including 10 bytes RAM is used to store information, RAM four bytes RAM time is us
Platform: | Size: 72704 | Author: ChenSheng | Hits:

[VHDL-FPGA-Verilog] BoXingFaSheng

Description: 多功能波形发生器VHDL程序与仿真 功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节量阶为1/51V）。 --其中方波的幅度还可通过u0、d0调节输出数据的归一化幅值（AMP0）进行进一步 --细调（调节量阶为1/（51*255）V）。方波A的占空比通过zu、zp按键调节（调节 --量阶1/64*T）。系统采用内部存储器——RAM实现任意输入波形的存储，程序只支 --持键盘式波形特征参数置入存储，posting 为进入任意波置入(set)、清除（clr）状态 --控制信号，SSS控制存储波形的输出。P180为预留端口 -Wave Generator
Platform: | Size: 10240 | Author: 梁辰 | Hits:

[VHDL-FPGA-Verilog] ram_sp_ar_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] ram_sp_sr_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] ram_dp_sr_sw.v

Description: this is a verilog source code for Dual Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[SCM] adda

Description: 文件名称: A/D实验--采样、存储和显示实验.ASM 文件标识: none 适用器件: 89C51 ①ADC0809的片选CS1连A15，RAM6116的片选CS3连A14。 ②要求在ADC0809的输入端加上不同的模拟信号，通过键盘输入ADC0809的通道号并启动A/D转换， 采集N个（如N=256）数据存入外部RAM中，打开XDATA窗口，检查实验结果。 注意：①在进行A/D采样前，应先检查ADC0809的参考电压是否正确。 （要求ADC0809的参考电压值Vref = +5V，用万用表观察ADC0809芯片的12脚电压值。 若不对，可调节实验板上的电位器W1来改变A/D的参考电压值）。 ②实验板上电位器W2可调节校准信号的值（注：实验板上校准信号已经连到通道7的IN7上）。 ③将AD采样的值送到RAM6116的0b000H开始单元中，同时在数码管上显示出来。 -File Name: A/D experiment- sampling, storage and display of experimental ASM File identification: none Applicable to devices: 89C51 ① the ADC0809 s chip select CS1 with A15-, A14, RAM6116 chip select CS3 even. The ② requirements with different analog signal input of the ADC0809, and start the channel number of the keyboard to enter the ADC0809 A/D converter, Acquisition of N (eg, N = 256) data are stored in external RAM, open the the XDATA window, check the experimental results. Note: ① The carrying out A/D sampling, you should first check ADC0809 reference voltage is correct. (For the ADC0809 reference voltage value Vref =+5 V, to observe the ADC0809 chip 12-pin voltage with a multimeter. If you are right, the experimental board adjustable potentiometer W1 to change the A/D reference voltage value). ② The board potentiometer W2 to adjust the value of the calibration signal (Note: The experimental on-board calibration signal is connected to channel 7 IN7). (3) the value of th
Platform: | Size: 1024 | Author: ilkb | Hits:

[VHDL-FPGA-Verilog] msp430x41x

Description: 低电源电压范围为1.8 V至3.6 V 超低功耗： - 主动模式：280μA，在1 MHz，2.2伏 - 待机模式：1.1μA - 关闭模式（RAM保持）：0.1μA 五省电模式 欠待机模式唤醒 超过6微秒 16位RISC架构， 125 ns指令周期时间 12位A/ D转换器具有内部 参考，采样和保持，并 AutoScan功能 16位Timer_B随着三† 或七‡ 捕捉/比较随着阴影寄存器 具有三个16位定时器A 捕捉/比较寄存器 片上比较器 串行通信接口（USART）， 选择异步UART或 同步SPI软件： - 两个USART（USART0 USART1）的† - 一个USART（USART0）‡ 掉电检测 电源电压监控器/监视器 可编程电平检测 串行板载编程， 无需外部编程电压 安全可编程代码保护 融合-Low Supply-Voltage Range, 1.8 V to 3.6 V Ultralow-Power Consumption: − Active Mode: 280 µ A at 1 MHz, 2.2 V − Standby Mode: 1.1 µ A − Off Mode (RAM Retention): 0.1 µ A Five Power Saving Modes Wake-Up From Standby Mode in Less Than 6 µ s 16-Bit RISC Architecture, 125-ns Instruction Cycle Time 12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature 16-Bit Timer_B With Three† or Seven‡ Capture/Compare-With-Shadow Registers 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software: − Two USARTs (USART0, USART1)† − One USART (USART0)‡ Brownout Detector Supply Voltage Supervisor/Monitor With Programmable Level Detection Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse
Platform: | Size: 1932288 | Author: 苏春明 | Hits:

[DSP program] FLASH

Description: DSP2407应用外部FLASH来进行调试或者使用外部RAM调试的例程分析比较。-DSP2407 USE FLASH TO TEST,VERY USEFUL FOR THE NEWER!PLEASE STUDY CAREFULY.AAA CCC BBB SSS SS DDD DDD V V .EWQEWQ DSDS DWDSD WDEWQEW WEWE WEEW ERWRWE EERWE EWEFE RYJ RGTRHT RGRGB TGTYU
Platform: | Size: 7168 | Author: 王燕红 | Hits:
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