Location:
Search - RISC DSP
Search list
Description: ARM7硬件说明与开发
The ARM7 is a low-power, general purpose 32-bit RISC microprocessor macrocell for use in application or
customer-specific integrated circuts (ASICs or CSICs). Its simple, elegant and fully static design is
particularly suitable for cost and power-sensitive applications. The ARM7’s small die size makes it ideal for
integrating into a larger custom chip that could also contain RAM, ROM, logic, DSP and other cells.-ARM7 hardware illustrated and developed The ARM7 is a low-power, general purpose 32-bit RISC microprocessor ma crocell for use in application or customer-spe cific integrated circuts (ASICs or CSICs). Its simple, elegant and fully static design is particularl y suitable for cost and power-sensitive applic ations. The ARM7's small die size makes it ideal for integrating into a larger custom chip that c ould also contain RAM, ROM, logic, DSP and other cells.
Platform: |
Size: 182892 |
Author: li zhuo |
Hits:
Description: 根据微机保护系统的发展趋势, 提出了一种基于数字信号处理器(DSP) 和高级RISC 微处理器(ARM) 双处
理器结构的数字继电保护硬件平台的设计方案,
Platform: |
Size: 74627 |
Author: 王超 |
Hits:
Description: ARM7硬件说明与开发
The ARM7 is a low-power, general purpose 32-bit RISC microprocessor macrocell for use in application or
customer-specific integrated circuts (ASICs or CSICs). Its simple, elegant and fully static design is
particularly suitable for cost and power-sensitive applications. The ARM7’s small die size makes it ideal for
integrating into a larger custom chip that could also contain RAM, ROM, logic, DSP and other cells.-ARM7 hardware illustrated and developed The ARM7 is a low-power, general purpose 32-bit RISC microprocessor ma crocell for use in application or customer-spe cific integrated circuts (ASICs or CSICs). Its simple, elegant and fully static design is particularl y suitable for cost and power-sensitive applic ations. The ARM7's small die size makes it ideal for integrating into a larger custom chip that c ould also contain RAM, ROM, logic, DSP and other cells.
Platform: |
Size: 182272 |
Author: li zhuo |
Hits:
Description: 根据微机保护系统的发展趋势, 提出了一种基于数字信号处理器(DSP) 和高级RISC 微处理器(ARM) 双处
理器结构的数字继电保护硬件平台的设计方案,-Microprocessor-based protection system in accordance with the development trend is proposed based on digital signal processor (DSP) and advanced RISC microprocessor (ARM) the structure of dual-processor hardware platform digital relay protection design scheme,
Platform: |
Size: 74752 |
Author: 王超 |
Hits:
Description: Omap2420适合基于Linux、Windows和Symbian操作系统(OS)的高端手机应用。它是Omap 2系列产品中的第一款，而Omap2系列最终将会转向“调制解调和应用处理器”的混合领域。或许这款芯片最吸引人的地方就是多处理器内核，它包含了330MHz的ARM 11 RISC、220 MHz的TI C55 DSP、内含ARM7的成像和视频处理器，以及支持166 MHz移动DDR SDRAM的Imagination Technologies公司3-D图形处理器。该芯片还集成了显示和相机控制器、SDRAM和闪存控制器，并附加了60多个外围控制器。Omap 2420能够为高端多媒体应用提供强大支持，这些应用包括30fps通用中间格式(CIF)的视频会议、30fps的VGA编解码、VGA和TV显示，以及300万像素以上的相机。使用该芯片的手机设计已经进行了一段时间，估计马上就会投放市场-OMP2420
Platform: |
Size: 83968 |
Author: yangyicai |
Hits:
Description: AT32UC0512技术资料，是目前最新版本，是高性能，低功耗AVR32UC 32位微控制器，精简单周期RISC指令集，含DSP指令集，高速内存FLASH 512KB和邵贝贝的书
-AT32UC0512 technical information, is the latest version of the high-performance, low power consumption AVR32UC 32-bit microcontroller, refined simple cycle RISC instruction set, instruction set with DSP, high-speed memory and FLASH 512KB book Shao Beibei
Platform: |
Size: 48964608 |
Author: 朱骏丰 |
Hits:
Description: 在现有的PSTN 网络上构建了一个嵌入式终端平台,该平台基于RISC 架构ARM 处理器S3C2440A,符合国际电联ITUT
建议的H.324 协议。此系统平台在原有的MCU+DSP 的架构基础上提出一种纯基于RISC 架构的ARM 处理器的可视电话
平台,该方案更加灵活, 可以用于现有的办公,家庭等环境.-Build a embedded platform of the ARM920T core RISC CPU S3C2440, which can connected to PSTN networks. This pure
RISC system comply with the ITU-T H.324, developed from the MCU+ASIC and the MCU+DSP architecture, is more flexible. The
VideoPhone based on this system could be widely used in the office and the house.
Platform: |
Size: 217088 |
Author: 张波 |
Hits:
Description: RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].
Platform: |
Size: 230400 |
Author: 朱伟成 |
Hits:
Description: PIC单片机C语言教程 包含大量实例程序 帮助初学者迅速入门 其中也介绍了数字信号处理DSP，可编程逻辑控制器PLC,高级精简指令处理器ARM-PIC Microcontroller C language tutorial contains a large number of example programs to help beginners started quickly, which also introduced digital signal processing DSP, programmable logic controller PLC, ARM Advanced RISC processor
Platform: |
Size: 147456 |
Author: kevin |
Hits:
Description: RISC与DSP的结构比较及在嵌入式应用中的方案选择-Structure comparison of RISC and DSP and embedded applications in the program selection
Platform: |
Size: 286720 |
Author: augusdi |
Hits:
Description: 常用ARM指令集及汇编
ARM（Advanced RISC Machines）是微处理器行业的一家知名企业，该企业设计了大量高性能、廉价、耗能低的RISC处理器、相关技术及软件。技术具有性能高、成本低和能耗省的特点，适用于多种领域，比如嵌入控制、消费/教育类多媒体、DSP和移动式应用等。
-ARM instruction set and compilation of commonly used ARM (Advanced RISC Machines) is the microprocessor industry, a well-known enterprises, the company designed a large number of high-performance, low-cost, low power consumption RISC processors, related technologies and software. Technology with high performance, low cost and power consumption characteristics of the province, for a variety of areas, such as embedded control, consumer/educational multimedia, DSP and portable applications.
Platform: |
Size: 1032192 |
Author: 狮子 |
Hits:
Description: tms320c6678 主要介绍了c66x的芯片功能，端口、控制器，封装，存储空间分布等-TI’s KeyStone Multicore Architecture provides a high-performance structure for integrating RISC and DSP cores
with application-specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
Platform: |
Size: 1965056 |
Author: 张染 |
Hits:
Description: ICCAD 2004 Faraday Mixed-size Benchmarks with routing information
Faraday Corp. recently released three benchmarks, originally intended
for comparisons between structured and conventional ASICs. We apply to
these benchmarks a standard ASIC design flow to generate five
mixed-size designs. Faraday benchmarks include three commonly-used
functional blocks: (I) 16-bit DSP, (II) 32-bit RISC CPU and (III)
DMA. Other details on these benchmarks such as the EDA Tools used by
Faraday, implementation conditions, settings etc. can be found in on
the faraday web-site. To minimize the impact of routing on the results
of the accounted placement approaches, we avoid clock-tree generation
and power routing in our flows. However, both clock-trees and power
rails can be built on theses benchmarks. Following is the description
of our ASIC flow which we used for generating the mixed-size
benchmarks from the original netlists.
Platform: |
Size: 7427884 |
Author: ahimsafollower@gmail.com |
Hits: