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Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
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Size: 865899 |
Author: 田晶昌 |
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Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: |
Size: 865280 |
Author: 田晶昌 |
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Description: RS编译码器的DSP实现，首先用MATLAB仿真，最后在DSP上实现-RS of DSP codecs to achieve, the first simulation using MATLAB, and finally realized in the DSP
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Size: 865280 |
Author: 小范 |
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Description: 内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等-There are 8-3 decoder, 8-bit adder, digital clock, digital display, 74ls138, 8,4 bit counter, d, rs flip-flops, adders, traffic lights, etc.
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Size: 905216 |
Author: fsdf |
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