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[Other] RS-RTOS-DEV

Description: 《强实时嵌入式系统开发》（Rev1.00）-"hard real-time embedded system development" (Rev1.00)
Platform: | Size: 1004544 | Author: super302 | Hits:

Description: rt-rtos,国人写的实时操作系统，值得研究，内附该rtos的设计文档，非常珍贵-rt-rtos, people write real-time operating system, worthy of study, containing the RTOS design document, very precious
Platform: | Size: 1281024 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[SCM] test

Description: A universal asynchronous receiver/transmitter, abbreviated UART ( /ˈ juː ɑrt/), is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS-232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods (such as differential signaling etc.) typically are handled by a special driver circuit external to the UART.
Platform: | Size: 135168 | Author: Den | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd，rt，rs sra rd，rt，shamt blez rs, imm j target lwl rt，offset（base） lwr rt，offset（base） lw rt，imm（rs） sw rt，imm（rs） -Written in Verilog HDL or VHDL language, multi-cycle CPU design. Able to complete the following 22 instructions. (Not taking into account the virtual address and the Cache, and the default is big endian): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
Platform: | Size: 5079040 | Author: 徐帆 | Hits:

[VHDL-FPGA-Verilog] mulitcpu

Description: 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset(base) lwr rt, offset(base) lw rt, imm(rs) sw rt, imm(rs) -Verilog HDL language or VHDL language to write multi-clock cycle of the CPU design. To complete the following 22 specified (not taking into account the virtual address and the Cache and the default Xiaoduan): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)Undo edits DictionaryGoogle Translate for Business:Translator ToolkitWebsite TranslatorGlobal Market Finder
Platform: | Size: 8877056 | Author: 徐帆 | Hits:

[VHDL-FPGA-Verilog] 091220111singalcpu

Description: 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, ts, imm blez rs, imm j target -Verilog HDL language or VHDL language to write the single-cycle CPU design. Able to complete the following 16 designated: add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, ts, imm blez rs, imm j target
Platform: | Size: 9529344 | Author: 徐帆 | Hits:

[JSP/Java] mips_pipeline_sim

Description: The simulator can run the following subset of the MIPS instruction set in the format described -> add $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> sub $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> and $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> or $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> slt $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> move $rd $rs [immediate value can be given instead of $rs & $rt] -> li $rd imm_val -> syscall -> lw $reg var_name -> sw $reg var_name -> beq $rs $rt label -> j label-The simulator can run the following subset of the MIPS instruction set in the format described -> add $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> sub $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> and $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> or $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> slt $rd $rs $rt [immediate value can be given instead of $rs & $rt] -> move $rd $rs [immediate value can be given instead of $rs & $rt] -> li $rd imm_val -> syscall -> lw $reg var_name -> sw $reg var_name -> beq $rs $rt label -> j label
Platform: | Size: 10240 | Author: Rage | Hits:

[hospital software system] structure

Description: 提取dicom RT文件中ROI的结构其中的image为RT中提取到的图像文件包括开始坐标维度等 path为路径 name为RS文件的名字(Extract the structure of the ROI in the DICOM RT file)
Platform: | Size: 1024 | Author: confina | Hits:

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