Search - RS232 CONTROLLER VHDL

Search - RS232 CONTROLLER VHDL - List

[VHDL-FPGA-Verilog] uart DL : 0: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Update : 2025-02-17 Size : 5kb Publisher : 陈想
[Com Port] b13c_environment DL : 0: rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores-rs232 controller rs232 to achieve the environmental settings, verilog prepared, owned by opencores
Update : 2025-02-17 Size : 62kb Publisher : uknow
[VHDL-FPGA-Verilog] 07_rs232_echo DL : 0: Controller RS232 in VHDL
Update : 2025-02-17 Size : 2kb Publisher : darek
[VHDL-FPGA-Verilog] Rs232sourcecode DL : 0: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Update : 2025-02-17 Size : 5kb Publisher : Ikki
[Driver Develop] Rs232_Recv2 DL : 0: controller RS232 for receiving serial data at different speeds
Update : 2025-02-17 Size : 1kb Publisher : Natacho
[Com Port] RS232_Controller DL : 0: This project is a RS232 Controller used to communicate two devices.
Update : 2025-02-17 Size : 494kb Publisher : Arley