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[Crack Hack] aes_8bit

Description: VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits-VHDL realize 128bitAES encryption algorithm LOW AREA realize cost-saving DATA FLOW for 8 bits
Platform: | Size: 19456 | Author: ZHUOHUI LI | Hits:

[VHDL-FPGA-Verilog] BasicRSA

Description: RSA加密算法的VHDL实现，通过实际FPGA验证。-RSA encryption algorithm of VHDL realize, through actual FPGA verification.
Platform: | Size: 9216 | Author: 张开文 | Hits:

[Crack Hack] khalil2006_true_random_number_generator

Description: a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are required to generate public/private key pairs for asymmetric algorithm such as RSA and symmetric algorithm such as AES.
Platform: | Size: 418816 | Author: Hassan Abdelaziz | Hits:

[Crack Hack] BasicRSA_latest.tar

Description: RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key
Platform: | Size: 5120 | Author: nb | Hits:

[Crack Hack] rsa

Description: 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
Platform: | Size: 2384896 | Author: 齐娜 | Hits:

[Other] rsa_latest.tar

Description: RSA VHDL 源代碼,僅供參考-RSA
Platform: | Size: 7168 | Author: hermann | Hits:

[Windows Develop] 7941955BasicRSA

Description: The RSA algorithm can be used for both public key encryption and digital signatures. Its security is based on the difficulty of factoring large integers. -The RSA algorithm can be used for both public key encryption and digital signatures. Its security is based on the difficulty of factoring large integers.
Platform: | Size: 9216 | Author: parvathalu | Hits:

[VHDL-FPGA-Verilog] Modular_Multiplier-modmult

Description: DEFINITELY FRUITFULL FOR RSA ENCRYPTION
Platform: | Size: 36864 | Author: HIMANSHU SINGH | Hits:

[VHDL-FPGA-Verilog] RSACypher

Description: FUITFULL FOR RSA ALGORITM IN VHDL
Platform: | Size: 45056 | Author: HIMANSHU SINGH | Hits:

[VHDL-FPGA-Verilog] rsa_IN_vhdl

Description: FULL SIMOLATION IN VHDL FOR RSA DECRYPTION
Platform: | Size: 2019328 | Author: HIMANSHU SINGH | Hits:

[VHDL-FPGA-Verilog] rsa

Description: FORFPGA IMPLEMENTATION OF RSA ALGORITHM USING HDL
Platform: | Size: 227328 | Author: HIMANSHU SINGH | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用vhdl语言实现了rsa算法功能，位宽可调-RSA
Platform: | Size: 7168 | Author: huyanzi | Hits:

[VHDL-FPGA-Verilog] RSA_Project

Description: encryption using RSA algorithm
Platform: | Size: 70656 | Author: hasan | Hits:

[VHDL-FPGA-Verilog] rsa.tar

Description: good working RSA code with testbench
Platform: | Size: 7168 | Author: veerender | Hits:

[Software Engineering] ECC2

Description: 椭圆曲线密码系统（点乘体系研究），可用于RSA密码体系-Elliptic Curve Cryptography (Multiplication System), can be used in RSA cryptosystem
Platform: | Size: 1295360 | Author: 余振华 | Hits:

[Crack Hack] rsalatest.tar

Description: rsa encryption using montegomery multiplication algorithm
Platform: | Size: 7168 | Author: Lakshman | Hits:

[VHDL-FPGA-Verilog] 12bitRSAencoderadecoder

Description: 我编写的一个12位rsa编码模块和解码模块，使用verilog模块-I wrote a 12-bit rsa encoding module and decoding module, use the verilog module
Platform: | Size: 2048 | Author: Gevy | Hits:

[VHDL-FPGA-Verilog] rsa_512_latest.tar

Description: 512位RSA VHDL 算法,使用了蒙哥马利模乘算法，该程序写的有些麻烦，但是对于初学者学习是够了。-512 bit RSA VHDL algorithm,it is open cores.it is very good for beginers to study.
Platform: | Size: 239616 | Author: 呼延郎 | Hits:

[VHDL-FPGA-Verilog] 512_RSA

Description: 512位RSA VHDL 算法,使用了蒙哥马利模乘算法，该程序写的有些麻烦，但是对于初学者学习是够了。-512 bit RSA VHDL algorithm,it is open cores.it is very good for beginers to study.
Platform: | Size: 13312 | Author: 呼延郎 | Hits:

[OS program] RSA-REPORT

Description: a simple VHDL program on RSA encryption technique
Platform: | Size: 101376 | Author: Prajoon | Hits:
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