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[ARM-PowerPC-ColdFire-MIPS] 第1章－SD卡读写模块 DL : 0: 第1章－SD卡读写模块 1. sdconfig.h: 该文件为SD卡读写模块配置头文件，用户可根据实际硬件条件进行修改. 2. SD目录 : SD卡读写模块的全部文件,一般不用修改. 3. 建议sdconfig.h文件不要放于SD目录中，因为SD目录中的文件一般无须修改,sdconfig.h通常会有改动. 4. 例子见上一级目录的SDExample目录.-Chapter 1-SD Card Reader module 1. Sdconfig.h : This document SD Card Reader module configuration files, users can be based on actual hardware changes. 2. SD Contents : SD Card Reader module all documents, generally need not be amended. 3. Recommendations sdconfig.h documents will not put SD directory because the directory SD generally no need to amend the document, sdconfig.h usually subject to change. 4. See above examples SDExample a directory of directories.
Update : 2025-02-17 Size : 165kb Publisher : k14789
[Other Embeded program] smartcard_vhdl DL : 1: SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2ascii.vhd binary2bcd.vhd lcd.vhd power_up.vhd-SD card reader of VHDLVHDL Source Files in Smartcard: Top.vhd- top level file smartcard.vhd conver2ascii.vhd binary2bcd.vhd lcd.vhd power_up.vhd
Update : 2025-02-17 Size : 411kb Publisher : gbh
[VHDL-FPGA-Verilog] FPGA-SD-COMMUNICATION DL : 0: 基于QUARTUSII软件实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信所用语言位verilog HDL-QUARTUSII software implementation based on FPGA (ATERA CYCLONE II series) with SD Card SD mode digital communication language verilog HDL
Update : 2025-02-17 Size : 4.83mb Publisher : chenbinjie
[SCM] sd-spi DL : 0: SD卡切换到SPI模式的工作流程，必须遵守这个流程-SD card SPI mode switch to the work flow, we must comply with the flow
Update : 2025-02-17 Size : 1kb Publisher : lsc
[Other] sd_IP DL : 0: SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck-SD card controller can just read data using 1 bit SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck
Update : 2025-02-17 Size : 8kb Publisher : tuya
[VHDL-FPGA-Verilog] main DL : 0: altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success
Update : 2025-02-17 Size : 1kb Publisher : 娟娟
[Embeded-SCM Develop] sd+spi DL : 0: sd 的spi模式详细的中文资料，一位好心人翻译的-sd of the spi mode in detail the information the Chinese, a translation of well-wishers
Update : 2025-02-17 Size : 1.74mb Publisher : 黄天乐
[Other] sd DL : 0: 自己做的数字逻辑电路课程设计，课题：八位二进制并行加法器的实现，包含代码和流程图以及基本说明-Themselves to do the digital logic circuit design, topics: 8 parallel binary adder realize that contains code and flow chart as well as basic instructions
Update : 2025-02-17 Size : 18kb Publisher : 小梦
[File Format] cbm3080_datasheet_v1.1 DL : 0: CBM3080芯片的使用说明，该芯片可以实现对SD卡的有效控制-CBM3080 chips for use, the chip can be achieved for the effective control of SD card
Update : 2025-02-17 Size : 702kb Publisher : 董小猪
[Windows Develop] SDIOCLK DL : 0: SDIO & SD spec上面所寫的做，每8個cycle讀一次，確定第一個bit是0，第二個bit是1，就接者讀剩下的46bit的CMD，讀完CMD，等 16cycle的空檔，再開始response，視CMD的不同，會有的response，回完response，就繼續等CMD。-SDIO
Update : 2025-02-17 Size : 3.62mb Publisher : wanlin su
[VHDL-FPGA-Verilog] SD_Host_Model_513_02 DL : 0: 可做SD的simulation model-SD can do the simulation model
Update : 2025-02-17 Size : 3.65mb Publisher : Arthur
[VHDL-FPGA-Verilog] sd_reader DL : 0: SD卡读卡器模块的VHDL及软件驱动代码，可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s-SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clock rate up to read 8MByte/s
Update : 2025-02-17 Size : 18kb Publisher : ctqy
[VHDL-FPGA-Verilog] sd_card DL : 0: 在开发FPGA上比较有用，主要关于SD CARD的源码-FPGA in the development of more useful, the main source of about SD CARD
Update : 2025-02-17 Size : 27.79mb Publisher : 田景
[Embeded Linux] neek_alternate_sd_card_controller DL : 0: This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).-This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).
Update : 2025-02-17 Size : 2.07mb Publisher : zhangdongqing
[VHDL-FPGA-Verilog] SD_card_src DL : 0: 一个基于VHDL语言的8位SD卡读取程序。含有源代码和说明-VHDL language based on an 8-bit SD card reader. Containing the source code and description
Update : 2025-02-17 Size : 20kb Publisher : 李超
[SCSI-ASPI] spi_Master DL : 0: 实现了对SD卡的SPI方式下读写操作，已经测试了，可以直接用-The realization of the SD card to read and write SPI operation mode has been tested, can be directly used
Update : 2025-02-17 Size : 2.02mb Publisher : 张立涛
[VHDL-FPGA-Verilog] SDCard_Controller DL : 0: SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 -SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
Update : 2025-02-17 Size : 24kb Publisher : xiafei
[VHDL-FPGA-Verilog] spimaster DL : 1: SPI IP core supporting SD/MMC
Update : 2025-02-17 Size : 2.16mb Publisher : zhanglh
[Communication-Mobile] sdcard_mass_storage_controller DL : 0: A host controlled ot control sd cards
Update : 2025-02-17 Size : 2.17mb Publisher : Anand Krishna
[VHDL-FPGA-Verilog] SD-card-controller-used--FPGA DL : 0: SD卡控制器的FPGA实现 -SD card controller FPGA to achieve SD card controller FPGA implementation
Update : 2025-02-17 Size : 251kb Publisher : liujie

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