Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M Platform: |
Size: 776192 |
Author:张涛 |
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Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference. Platform: |
Size: 776192 |
Author:汪旭 |
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Description: sdram控制器的开发程序,还有文档,可以参考以下-SDRAM controller development process, there is a document, you can refer to the following Platform: |
Size: 776192 |
Author:王鹏 |
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Description: 标准SRD SDRAM控制器参考设计,altera提供
Verilog代码,带有使用手册,大家试试交流一下
-Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some Platform: |
Size: 776192 |
Author:费尔德 |
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Description: 基于VHDL编写的SDR-SDRAM控制器的编程,目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller Platform: |
Size: 1013760 |
Author:wfs |
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Description: this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block Platform: |
Size: 2048 |
Author:Taher Aghazadeh |
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Description: altera 公司sdr sdram 控制器源码,是VHDL的,大家选择下载-The altera sdr sdram controller source, the VHDL, we choose to download Platform: |
Size: 16384 |
Author:梦殇 |
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Description: 说明: SDR SDRAM 控制器 来自lattice 已经分析代码可用!大家可以参考修改,形成自己的实例(Description: SDR SDRAM controller from lattice has been analyzed code available, we can refer to modify, to form their own examples) Platform: |
Size: 17408 |
Author:modelsim
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