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[Communication] Pcidriver

Description: PCI驱动编程实例，通过PCI可实施操作： 2、通过DMA方式往SDRAM写数据的步骤： (1) 往OMB1写传输数据次数 (2) 往OMB2写所要访问的SDRAM地址 (3) 往FIFO写2 3、通过DMA方式从SDRAM读数据的步骤： (1) 往OMB1写传输数据次数 (2) 往OMB2写所要访问的SDRAM地址 (3) 往FIFO写3 -PCI-driven programming examples, can be implemented through the PCI operation : 2, DMA SDRAM write data to the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to FIFO write 2 3 through DMA side SDRAM-time data from the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to write FIFO 3
Platform: | Size: 62751 | Author: 葛琳 | Hits:

[Other resource] vga.niosII.compent.v

Description: 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
Platform: | Size: 6599 | Author: Ray ZH | Hits:

[USB develop] USB and SDRAM Controller

Description: 基于CY7C68013A的Slave FIFO和SDRAM控制器
Platform: | Size: 10313628 | Author: xjtuzhangx@163.com | Hits:

[Program doc] Pcidriver

Description: PCI驱动编程实例，通过PCI可实施操作： 2、通过DMA方式往SDRAM写数据的步骤： (1) 往OMB1写传输数据次数 (2) 往OMB2写所要访问的SDRAM地址 (3) 往FIFO写2 3、通过DMA方式从SDRAM读数据的步骤： (1) 往OMB1写传输数据次数 (2) 往OMB2写所要访问的SDRAM地址 (3) 往FIFO写3 -PCI-driven programming examples, can be implemented through the PCI operation : 2, DMA SDRAM write data to the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to FIFO write 2 3 through DMA side SDRAM-time data from the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to write FIFO 3
Platform: | Size: 62464 | Author: 葛琳 | Hits:

[VHDL-FPGA-Verilog] FIFO_BEFORE

Description: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Platform: | Size: 211968 | Author: eva | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
Platform: | Size: 717824 | Author: 吴厚航 | Hits:

[Special Effects] image-FIFO-SDRAM

Description: 图像缓存是图像处理系统设计的重点和难点，包括SDRAM和FIFO的设计，本PDF是设计图像缓存设计的好资料-sdram and fifo design for real-time image processing system
Platform: | Size: 1146880 | Author: 张荣奎 | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[DSP program] DSP6713

Description: 包括定时器、SPI、SDRAM、Flash、FIFO等程序，均调试通过-SPI\SDRAM\Flash\FIFO\timer for DSP6713
Platform: | Size: 916480 | Author: HYD | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s internal logic to realize the ADC, SDRAM, LAN controller chip DM9000 timing control to capture FPGA as the core of the system, through the ADC, will be collected The data stored in SDRAM, the SDRAM in order to read data from the FIFO method, and data results to a computer via Ethernet interface
Platform: | Size: 388096 | Author: gdr | Hits:

[VHDL-FPGA-Verilog] sdram

Description: SDRAM ctrller 用于SDRAM控制器的读写控制，利用4个 FIFO实现读写数据的缓存。-sdram ctrl
Platform: | Size: 186368 | Author: 张朋 | Hits:

[DSP program] rty

Description: 近年来，随着DSP的快速发展，被广泛的应用于图像处理及目标定位[11][13][21]上，极大地提高图像处理的实时性。DSP主要用来实现扩展算法和数字信号处理的功能，其最典型的用途是实现数字图像处理算法。DSP芯片内采用大容量的SRAM作为系统的高速缓存，高达64位的数据总线带宽。在片外采用了目前流行的SDRAM、DDR2等高速大容量存储器的无缝连接，同时还支持SRAM、FIFO等各种类型的存储器，大大提高了图像的存储容量及速度。-In recent years, with the rapid development of DSP, has been widely used in image processing and target location [11] [13] [21], and greatly improve the image processing in real time. Mainly used to implement DSP algorithms and digital signal processing expansion of the function, the most typical use digital image processing algorithms. DSP chip with large-capacity SRAM cache as a system, up to 64-bit data bus bandwidth. Chip used in the popular SDRAM, DDR2 memory and other high-speed large-capacity seamless connection, and also supports SRAM, FIFO, and other types of memory, greatly improving the image storage capacity and speed.
Platform: | Size: 261120 | Author: 侯国强 | Hits:

[Special Effects] s

Description: 近年来，随着DSP的快速发展，被广泛的应用于图像处理及目标定位[11][13][21]上，极大地提高图像处理的实时性。DSP主要用来实现扩展算法和数字信号处理的功能，其最典型的用途是实现数字图像处理算法。DSP芯片内采用大容量的SRAM作为系统的高速缓存，高达64位的数据总线带宽。在片外采用了目前流行的SDRAM、DDR2等高速大容量存储器的无缝连接，同时还支持SRAM、FIFO等各种类型的存储器，大大提高了图像的存储容量及速度。-In recent years, with the rapid development of DSP, has been widely used in image processing and target location [11] [13] [21], and greatly improve the image processing in real time. Mainly used to implement DSP algorithms and digital signal processing expansion of the function, the most typical use digital image processing algorithms. DSP chip with large-capacity SRAM cache as a system, up to 64-bit data bus bandwidth. Chip used in the popular SDRAM, DDR2 memory and other high-speed large-capacity seamless connection, and also supports SRAM, FIFO, and other types of memory, greatly improving the image storage capacity and speed.
Platform: | Size: 1499136 | Author: 侯国强 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于Quartus平台利用SDRAM芯片设计FIFO 使数据能够高速写入 低速读出-Quartus platform based on the use of SDRAM chip design data to enable high-speed FIFO read write speed
Platform: | Size: 27648 | Author: 邬储 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: sdram，在fpga数据传递领域应用广泛，乒乓操作，不同频域的数据传递，都靠sdram来转换。-SDRAM VHDL FPGA FIFO
Platform: | Size: 2058240 | Author: 梁 | Hits:

[VHDL-FPGA-Verilog] test_sdram

Description: 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block, logic block read SDRAM, SDRAM modules package to read and write, read and write buffer FIFO module, serial module occurs. Altera-based engineering design of the Quartus II 10.1, the software can be used later.
Platform: | Size: 3128320 | Author: | Hits:

[VHDL-FPGA-Verilog] vhdl-Language-routine-highlights

Description: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Platform: | Size: 291840 | Author: shujian | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO先进先出，控制时序，对urat、SDRAM、DAC等时序理解都有帮助-FIFO FIFO control the timing of urat, SDRAM, DAC and other timing understanding have helped
Platform: | Size: 6571008 | Author: 刘佳益 | Hits:

[VHDL-FPGA-Verilog] SDRAM缓冲测试程序

Description: 对FPGA的SDRAM进行测试，主要是实现FIFO-SDRAM-FIFO的数据传输(Test the SDRAM of the FPGA)
Platform: | Size: 76057600 | Author: 降落 | Hits:
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