Description: 同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用-Synchronous Dynamic RAM control circuit VHDL source code, in the SOC development can be applied directly Platform: |
Size: 90112 |
Author:26 |
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Description: verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件-Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation Platform: |
Size: 19935232 |
Author:ch |
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Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O Platform: |
Size: 132096 |
Author:xbl |
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Description: It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit- Diligent fully working. Platform: |
Size: 1488896 |
Author:under |
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Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is Verilog.
This code is based Xilinx FPGA Playform. Platform: |
Size: 488448 |
Author:peace |
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Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。
debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考
RTL Coding and Optimization Guide for use with Design Compiler.pdf
数提讲座（1）.wmv
数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。
ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。
基于DDR SDRAM控制时序分析的模型.pdf
全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。
数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真.
-i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference.
debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference
RTL Coding and Optimization Guide for use with Design Compiler.pdf
Mention the number of lectures (1). Wmv
Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look.
ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese .
DDR SDRAM control the timing analysis based on the model. Pdf
Platform: |
Size: 20989952 |
Author:喻琪 |
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Description: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code Platform: |
Size: 291840 |
Author:shujian |
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