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[Other resource] Xilinx公司网站下的SDRAM Controller的参考设计 DL : 0: Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated
Update : 2008-10-13 Size : 125.39kb Publisher : 于飞
[SourceCode] altera sdram controller DL : 1: altera sdram controller vhdl
Update : 2011-03-17 Size : 2.26mb Publisher : langzhongfeilang@126.com
[VHDL-FPGA-Verilog] sdram_vhdl_lattice DL : 0: lattice sdram 控制器VHDL源代码-Sound code of Lattice Sdram Controller based on VHDL
Update : 2025-02-17 Size : 176kb Publisher : 刘汉忠
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2025-02-17 Size : 1007kb Publisher : 包盛花
[VHDL-FPGA-Verilog] Xilinx公司网站下的SDRAM Controller的参考设计 DL : 0: Update : 2025-02-17 Size : 125kb Publisher : 于飞
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] 标准SDR SDRAM控制器参考设计_verilog_lattice DL : 0: 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
Update : 2025-02-17 Size : 199kb Publisher : 陈旭
[VHDL-FPGA-Verilog] sdr sdram controller DL : 0: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Update : 2025-02-17 Size : 2.34mb Publisher : 陈东平
[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog DL : 0: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Update : 2025-02-17 Size : 758kb Publisher : 汪旭
[VHDL-FPGA-Verilog] sdram DL : 0: sdram控制器这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Update : 2025-02-17 Size : 3kb Publisher : 林博
[VHDL-FPGA-Verilog] sdram_control_burst DL : 0: 精简的sdram读写控制器例子，适用于数据采集系统，verilog，只支持burst方式的读写-streamlined read and write SDRAM controller example, applied to the data acquisition system, Verilog. only supports burst mode read and write
Update : 2025-02-17 Size : 150kb Publisher : 梁文锋
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[Other] AlteraSDRAMControllerWhitePaper DL : 0: Altera SDRAM Controller 白皮书，很详细的文档-Altera SDRAM Controller White Paper, a very detailed document
Update : 2025-02-17 Size : 685kb Publisher : wood
[VHDL-FPGA-Verilog] very-good-ok-ref-ddr-sdram-verilog DL : 0: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Update : 2025-02-17 Size : 874kb Publisher : 姚明
[Embeded-SCM Develop] SDRAM DL : 0: SDRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board
Update : 2025-02-17 Size : 1.5mb Publisher : 李大同
[VHDL-FPGA-Verilog] sdram DL : 0: sdram controller.verilog
Update : 2025-02-17 Size : 13kb Publisher : 刘志刚
[VHDL-FPGA-Verilog] AlteraSDR-SDRAM DL : 0: Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Update : 2025-02-17 Size : 792kb Publisher : machenghai
[Other] SDR-SDRAM-ctl1 DL : 0: SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
Update : 2025-02-17 Size : 702kb Publisher :
[VHDL-FPGA-Verilog] SDRAM-controller-design-FPGA-based DL : 0: 基于FPGA的SDRAM控制器设计及应用硕士论文-SDRAM controller design FPGA based
Update : 2025-02-17 Size : 3.02mb Publisher : connie
[VHDL-FPGA-Verilog] sdram controller DL : 2: Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst cycle. This reference design provides the user with a baseline SDRAM Controller design. The user may modify the design to meet specific design requirements. This document provides information on how this design operates and shows the user where changes can be made to support other functionality.
Update : 2025-02-17 Size : 8kb Publisher : Robuster

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