Search - SINE WAVE HDL

[VHDL-FPGA-Verilog] dds_vhdl

Description: dds的vhdl实现,主要包括正弦波、三角波和锯齿波的产生-dds achieve the VHDL, including sine, triangle wave, and the selection ramp
Platform: | Size: 1024 | Author: xxx | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
Platform: | Size: 87040 | Author: 黎明 | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] DDS234

Description: 文中给出了用VHDL实现三角波正弦波方波的代码, 可以在maxPLUX2上运行,-In this paper, using the VHDL-wave sine wave square wave triangle realize the code, you can run maxPLUX2,
Platform: | Size: 2048 | Author: qibinchuan | Hits:

[Embeded-SCM Develop] ad9851-1

Description:
Platform: | Size: 590848 | Author: 两鬓 | Hits:

[VHDL-FPGA-Verilog] sinwave

Description: 用verilog HDL产生正弦阶梯波。加da即可输出正弦波-Using verilog HDL ladder generated sine wave. Da can increase the output sine wave
Platform: | Size: 1024 | Author: chenmao | Hits:

[VHDL-FPGA-Verilog] DDS-top

Description: 能够基于DDS实现输出正弦波形的一部分程序，利用Verilog HDL语言编写。-Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
Platform: | Size: 299008 | Author: evil | Hits:

[VHDL-FPGA-Verilog] sWave

Description: 正弦波，Verilog波形发生器，很好的东西-Sine wave, Verilog waveform generator, a good thing
Platform: | Size: 1391616 | Author: yanppf | Hits:

[VHDL-FPGA-Verilog] FPGArealiztionofdigitalsignalprocessing

Description: 数字信号处理FPGA实现实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHDL代码的程序 cic.exe ---CIC滤波器计算参数的程序 -Digital Signal Processing FPGA realization of practical procedures and documents, there are sine.exe--- input width. Sine wave output of the corresponding csd.exe--- Table mif file to find the integer and fractional number of the volume of standard symbols (canonical signed digit, CSD) Expression Programming fpinv.exe--- countdown procedures for calculation of floating-point form dagen.exe--- documents distributed algorithm to generate HDL " onclick =" tagshow (event) " class =" t_tag " > VHDL program code cic.exe--- CIC filter process parameters
Platform: | Size: 260096 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] EPM240_SCH_and_program

Description: EPM240 cpld 原理图+程序。 Verilog HDL语言。程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。-Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display program, counters and so on.
Platform: | Size: 660480 | Author: student88 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
Platform: | Size: 117760 | Author: tiancheng | Hits:

[VHDL-FPGA-Verilog] DDS_FINAL

Description: My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency. We can change the frequency using frequency selector input. Please accept this project. We use the SPARTAN 3E 500 device to implement it.
Platform: | Size: 437248 | Author: Raju Kumar | Hits:

[Compress-Decompress algrithms] asias_dds

Description: 一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency
Platform: | Size: 31744 | Author: david | Hits:

[VHDL-FPGA-Verilog] dds_final

Description: 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Platform: | Size: 1638400 | Author: nostalgia | Hits:

[VHDL-FPGA-Verilog] waveform

Description: Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形-Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform
Platform: | Size: 2274304 | Author: saln | Hits:

[VHDL-FPGA-Verilog] Verilog-hdlFPGA

Description: 关于FPGA的提高篇，Verilog HDL语言写的，包含LCD控制VHDL程序与仿真，AD/DA，MASK，FSK，PSK，正弦波发生器，等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and VHDL simulation, AD/DA, MASK, FSK, PSK, sine wave generator, and so the classic procedure
Platform: | Size: 1181696 | Author: chenfeihu | Hits:

[VHDL-FPGA-Verilog] fankuizhendang

Description: 本程序是基于verilog HDL语言设计的反馈震荡电路的程序。其构成的电路叫振荡电路。能将直流电转换为具有一定频率交流电信号输出的电子电路或装置。种类很多，按振荡激励方式可分为自激振荡器、他激振荡器；按电路结构可分为阻容振荡器、电感电容振荡器、晶体振荡器、音叉振荡器等；按输出波形可分为正弦波、方波、锯齿波等振荡器。-This program is a feedback oscillator circuit design based on Verilog HDL language program. Constitute a circuit called the oscillation circuit. Able to convert DC to a certain frequency AC signal output of the electronic circuit or device. Many different types of oscillation excitation can be divided into self-excited oscillator excited oscillator RC oscillator, the inductor-capacitor oscillator, crystal oscillator, a tuning fork oscillator circuit structure can be divided into output waveform can be divided into sine wave, square wave, sawtooth oscillator.
Platform: | Size: 91136 | Author: 李炳旭 | Hits:

[VHDL-FPGA-Verilog] sinwave

Description: 使用verilog hdl语言编程正弦波信号，能仿真出结果-Can use verilog HDL language programming sine wave signal, the simulation results
Platform: | Size: 4291584 | Author: hxj | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用Verilog HDL 编写的一个最基本的DDS程序，发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
Platform: | Size: 890880 | Author: 董航 | Hits:

[Documents] 三角函数的Verilog HDL语言实现

Description: 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)
Platform: | Size: 148480 | Author: 所罗门 | Hits:

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[VHDL-FPGA-Verilog] dds_vhdl

[VHDL-FPGA-Verilog] ddfs

[Embeded-SCM Develop] DDSforsinandcos

[VHDL-FPGA-Verilog] DDS234

[Embeded-SCM Develop] ad9851-1

[VHDL-FPGA-Verilog] sinwave

[VHDL-FPGA-Verilog] DDS-top

[VHDL-FPGA-Verilog] sWave

[VHDL-FPGA-Verilog] FPGArealiztionofdigitalsignalprocessing

[VHDL-FPGA-Verilog] EPM240_SCH_and_program

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS_FINAL

[Compress-Decompress algrithms] asias_dds

[VHDL-FPGA-Verilog] dds_final

[VHDL-FPGA-Verilog] waveform

[VHDL-FPGA-Verilog] Verilog-hdlFPGA

[VHDL-FPGA-Verilog] fankuizhendang

[VHDL-FPGA-Verilog] sinwave

[VHDL-FPGA-Verilog] DDS

[Documents] 三角函数的Verilog HDL语言实现

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