Search - SPI CPLD

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[Other resource] PC104-CPLD-SPI DL : 1: VxWorks下PC104-CAN驱动程序设计,系统的基本功能是通过CPLD 来实现PC/104 总线SPI 总线的数据交换
Update : 2008-10-13 Size : 138.84kb Publisher : pangbai
[Documents] FPGA实现SPI DL : 0: 串行外设接口（SPI） cpld 被动接收
Update : 2011-12-26 Size : 35kb Publisher : gzdly@126.com
[VHDL-FPGA-Verilog] SPI_VHDL DL : 0: SPI串口的内核实现（vhdl）,可以用qII等软件直接加到FPGA或者CPLD里面.-the SPI Serial Kernel (vhdl) can be used directly qII software foisted CPLD or FPGA inside.
Update : 2025-02-17 Size : 13kb Publisher : efly
[Embeded-SCM Develop] vspi_VHDL DL : 0: FPGA/CPLD VHDL语言实现SPI，拥有两种模式，FPGA/CPLD即可工作在主机模式，又可工作在从机模式 -FPGA/CPLD VHDL language SPI, have the two models, FPGA/CPLD can work in host mode, but also work in slave mode
Update : 2025-02-17 Size : 243kb Publisher : 张焱
[VxWorks] PC104-CPLD-SPI DL : 0: Update : 2025-02-17 Size : 139kb Publisher : pangbai
[Embeded-SCM Develop] vhdlthreelinespi DL : 0: ＳＰＩ总线与ＣＰＬＤ之间的通信程序，可实现ＳＰＩ串行输入，通过移位寄存器后并行输出-SPI bus and the CPLD communication between these procedures is to realize SPI serial input, through the shift register parallel output after
Update : 2025-02-17 Size : 1kb Publisher : 金臻炜
[VHDL-FPGA-Verilog] spi_master DL : 0: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Update : 2025-02-17 Size : 1kb Publisher : linsky
[VHDL-FPGA-Verilog] an485_design_example DL : 0: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Update : 2025-02-17 Size : 305kb Publisher : zhiqiang
[Other] mcu+CPLD DL : 0: 嵌入式工程师必要的参考材料。mcu 和 CPLD 综合运用 ,有大量实例-Embedded engineers necessary reference material. mcu and comprehensive use of CPLD, a large number of examples
Update : 2025-02-17 Size : 7.59mb Publisher : cruise
[SCM] mcu-cpld-spi DL : 0: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
Update : 2025-02-17 Size : 108kb Publisher : 叶灿
[Embeded-SCM Develop] AIC DL : 0: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Update : 2025-02-17 Size : 2kb Publisher : 张键
[VHDL-FPGA-Verilog] SPI_IIC_design_example DL : 0: ALTERA原厂提供的例程，网上很难找到的，在MAX2系列芯片上实现过，VHDL和VERILOG两种语言编写 IIC读写程序-ALTERA provided the original routine, it is difficult to find online and in the MAX2 series chip-off, VHDL and VERILOG two languages
Update : 2025-02-17 Size : 385kb Publisher : 郑康山
[VHDL-FPGA-Verilog] slave_spi_ctrl DL : 1: SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集-SPI control course code
Update : 2025-02-17 Size : 1kb Publisher : luxiaogang
[VHDL-FPGA-Verilog] spi.sim DL : 0: vhdl spi cpld simulation
Update : 2025-02-17 Size : 4kb Publisher : mohamad
[VHDL-FPGA-Verilog] spi.tan DL : 0: vhdl spi cpld fpga cofiguration
Update : 2025-02-17 Size : 6kb Publisher : mohamad
[Applications] CPLD DL : 0: ad采集的小模块，实现串口转并口的功能，串口是SPI的接口-ad collector modoudle ad ad ad ad ad da da da da shuzi moni moni shuzi caiji caiji caiji caiji caiji caiji caiji
Update : 2025-02-17 Size : 32kb Publisher : ninglige
[VHDL-FPGA-Verilog] spi DL : 0: 基于CPLD的用SPI控制pwm的源码，用VHDL编写，已经测试，可以直接使用
Update : 2025-02-17 Size : 1kb Publisher : DRzhou
[DSP program] DA DL : 0: 00IC2407＋CPLD板上选用的DA转换器是TI公司的TLC5620,TLC5620是串行4通道8位 DA 转换器，DSP 通过 SPI 与其接口，TLC5620 的工作频率是 1MHZ,所有 DSP 的 SPI也必须设置位1MHZ, -00IC2407+ CPLD DA converter board is selected TI' s TLC5620, TLC5620 is a serial 4-channel 8-bit DA converters, DSP and its interface, through the SPI, TLC5620 operating frequency is 1MHZ, all the DSP' s SPI must also be set bit 1MHZ,
Update : 2025-02-17 Size : 66kb Publisher : lizhenli
[VHDL-FPGA-Verilog] cpld_spi DL : 0: cpld spi ，功能基本上满足普通项目的使用，欢迎使用。-cpld spi, function essentially to meet the general project use, Welcome.
Update : 2025-02-17 Size : 1.01mb Publisher : liliugang
[VHDL-FPGA-Verilog] spi_vhdl DL : 0: vhdl实现spi可以同有SPI接口的器件进行通信对SPI接口器件的读写控制vhdl源程序，fpga cpld-vhdl spi can achieve devices with a SPI interface to communicate with devices on the SPI interface to read and write vhdl source code control
Update : 2025-02-17 Size : 6kb Publisher : 站长

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