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[SCM] cc03-demo-spi-0_0_1

Description: MP3 spi Master例子程序-MP3 spi Master example procedure
Platform: | Size: 26624 | Author: 张仁峰 | Hits:

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[SCM] SPI

Description: mega16 spi主从通信 测试通过（ICC）-mega16 spi master-slave communications test through the (ICC)
Platform: | Size: 49152 | Author: 李建朋 | Hits:

[Embeded-SCM Develop] spiinterfaceverilog

Description: SPI Master Core Specification，This document provides specifications for the SPI (Serial Peripheral Interface) Master core-SPI Master Core Specification, This document provides specifications for the SPI (Serial Peripheral Interface) Master core
Platform: | Size: 82944 | Author: 贾远鸿 | Hits:

[SCM] EVB9S12XF512E_Node1_LS

Description: 基于freescale MC9S12XF512 MCU，芯片自带Flexray通信控制器。可实现高达10Mb/s的Flxray通信.本程序主要功能： 1) 500ms实时中断。 2) SPI MASTER 运行于500kHz。 3) Flexray 总线以1.25Mbit/s 通信。-Based on freescale MC9S12XF512 MCU, chip communications controller Flexray own. Can achieve up to 10Mb/s communication of Flxray. This procedure main functions: 1) 500ms real-time interrupt. 2) SPI MASTER running on 500kHz. 3) Flexray bus to 1.25Mbit/s communications.
Platform: | Size: 798720 | Author: 阿昆 | Hits:

[SCM] SPI

Description: 新华龙单片机SPI通信代码经过测试，保证能用，包括SPI存储器读写，主从模式通信-New single-chip SPI communication code hualong tested to ensure the use, including memory read and write SPI, master-slave mode of communication
Platform: | Size: 12288 | Author: 冯永刚 | Hits:

[Com Port] spi

Description: SPI master的verilog代码-Verilog code for SPI master
Platform: | Size: 2048 | Author: xudong | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[Embeded-SCM Develop] spi_core_open

Description: SPI 设计 为主机设计，供大家参考,希望对大家有用-SPI master design
Platform: | Size: 96256 | Author: 迪 | Hits:

[SCM] SPI

Description: 这是MC9S12DG128单片机SPI通讯模块开发实例,该实例包含SPI主从机的全部源代码,可实现双机通讯。-This is the MC9S12DG128 MCU SPI communication module development instance of SPI master and slave machines with all the source code, enabling two-machine communication.
Platform: | Size: 548864 | Author: Boolean | Hits:

[MPI] spi_verilog

Description: 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
Platform: | Size: 45056 | Author: davi_insist | Hits:

[SCM] spi.c

Description: tested on an STK500 with an ATmega32 with a 14.7456MHz crystal. Purpose: SPI init, read & write routines without interrupt. These routines works only as an SPI Master.-tested on an STK500 with an ATmega32 with a 14.7456MHz crystal. Purpose: SPI init, read & write routines without interrupt. These routines works only as an SPI Master.
Platform: | Size: 1024 | Author: akhilesh kumar | Hits:

[VHDL-FPGA-Verilog] l1ghVhVI

Description: The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
Platform: | Size: 226304 | Author: aaa | Hits:

[SCM] SPI

Description: c8051f120的spi接收发送 主从机模式-c8051f120 the spi master and slave mode of transmission received
Platform: | Size: 12288 | Author: 夜星辰 | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
Platform: | Size: 290816 | Author: 阿虎 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: verilog SPI master 的完整实验报告 仅供参考 切勿抄袭-verilog SPI master
Platform: | Size: 45056 | Author: ying ma | Hits:

[VHDL-FPGA-Verilog] Nitro-Parts-lib-SPI-master

Description: Nitro-Parts-lib-SPI Verilog SPI master and slave
Platform: | Size: 5120 | Author: d.pershin | Hits:

[Other] spi_masterSPI Master 的Verilog源代码

Description: 实现SPI主站通信功能,感兴趣的可以下载。(spi master use verilog.)
Platform: | Size: 133120 | Author: wenyiwenni | Hits:
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