Search - SPI VHDL

Search - SPI VHDL - List

[MPI] SPI-PRT DL : 0: 昨天在论坛上看到有人帖出了他写的并串转换VHDL代码，但是他自己说有问题，但是不知道怎么改。我大概看了一下，发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably watched and found ideas is quite a mess. So I wrote on their own code and string conversion.
Update : 2025-02-17 Size : 1kb Publisher : ZHAOBOO
[VHDL-FPGA-Verilog] CUS_SPI-VHDL DL : 0: 此为VHDL的SPI通信代码，全部在一个压缩包中，请仔细阅读后再使用．-this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
Update : 2025-02-17 Size : 4kb Publisher : 藏瑞
[VHDL-FPGA-Verilog] SPI DL : 0: SPI BUS VHDL实现-VHDL SPI BUS
Update : 2025-02-17 Size : 833kb Publisher : davidluo
[Other] spi DL : 0: VHDL 实现的SPI接口，在Altera EMP7128 上应用过-VHDL SPI interface, the application of Altera EMP off
Update : 2025-02-17 Size : 1kb Publisher : 陈同
[VHDL-FPGA-Verilog] spi DL : 0: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Update : 2025-02-17 Size : 64kb Publisher : 阿飞
[VHDL-FPGA-Verilog] spi DL : 0: SPI总线，VHDL语言，硬件描述语言源码-SPI bus, VHDL language, hardware description language source code
Update : 2025-02-17 Size : 3kb Publisher : 郑文棋
[VHDL-FPGA-Verilog] spi.tar DL : 0: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Update : 2025-02-17 Size : 114kb Publisher : hcjian
[SCM] SPI DL : 0: // This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
Update : 2025-02-17 Size : 71kb Publisher : 蓝天
[VHDL-FPGA-Verilog] spi DL : 0: spi协议的FPGA实现(Verlog).-spi protocol FPGA realize (Verlog).
Update : 2025-02-17 Size : 1kb Publisher : 徐凯
[VHDL-FPGA-Verilog] spi DL : 0: 用vhdl编写的spi接口程序，在epm7128上仿真成功。-VHDL prepared using spi interface program, in the simulation epm7128 success.
Update : 2025-02-17 Size : 1kb Publisher : 邓立新
[VHDL-FPGA-Verilog] VHDL DL : 1: VHDL程序集锦，很多有用程序，英文版其中有汉明码编译码，优先译码等等。-VHDL Collection procedures, many useful procedures, the English version of them hamming code encoding and decoding, the priority decoder and so on.
Update : 2025-02-17 Size : 165kb Publisher : 萍果
[Embeded-SCM Develop] sd+spi DL : 0: sd 的spi模式详细的中文资料，一位好心人翻译的-sd of the spi mode in detail the information the Chinese, a translation of well-wishers
Update : 2025-02-17 Size : 1.74mb Publisher : 黄天乐
[VHDL-FPGA-Verilog] spi DL : 0: 一篇比较好的spi接口的vhdl实现的参考-A relatively good spi interface realize VHDL reference
Update : 2025-02-17 Size : 18kb Publisher : 杨子树
[VHDL-FPGA-Verilog] SPI DL : 0: SPI经典ip核可以直接用于工程的开发和利用-err
Update : 2025-02-17 Size : 48kb Publisher : 毋杰
[Embeded-SCM Develop] SPI DL : 0: spi slave model spi slave model
Update : 2025-02-17 Size : 1kb Publisher : jason
[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc DL : 0: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Update : 2025-02-17 Size : 37kb Publisher :
[VHDL-FPGA-Verilog] SPI DL : 0: 用VHDL语言写出SPI,内含资料和代码-VHDL language used to write SPI, containing data and code
Update : 2025-02-17 Size : 48kb Publisher : th
[VHDL-FPGA-Verilog] spi DL : 0: spi的FPGA驱动用于嵌入式开发系统-spi the FPGA-driven development for embedded systems
Update : 2025-02-17 Size : 284kb Publisher : 田辉
[VHDL-FPGA-Verilog] SPI-Collect DL : 0: 一个spi串口希望大家能用上 -Spi serial a hope that we can use on
Update : 2025-02-17 Size : 1.27mb Publisher : hehe520
[VHDL-FPGA-Verilog] spi-vhdl DL : 0: 用vhdl写的spi通信，arm为主设备，fpga为从设备，其中包括代码，以及具体协议-failed to translate
Update : 2025-02-17 Size : 252kb Publisher : 欧翔

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