Search - SRAM core

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[VHDL-FPGA-Verilog] generic_avalon_sram DL : 0: 一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
Update : 2025-02-17 Size : 5kb Publisher : 林盈
[Other Embeded program] SRAM_16Bit_512K DL : 0: DE2板子附带的SRAM IPCORE 有兴趣的朋友可以下载-DE2 board attached SRAM IPCORE friends who are interested can download
Update : 2025-02-17 Size : 11kb Publisher : huang
[Other Embeded program] SRAMCotroller DL : 0: 一个SRAM控制器的IP核，很不错，有兴趣的朋友可以下去-An SRAM controller IP core, very good friends who are interested can go on
Update : 2025-02-17 Size : 315kb Publisher : liufanyu
[Other] IVSEP3203F50UserDataSheet DL : 0: 东芯IVSEP3203F50移动终端应用处理器用户手册第1 章东芯IV SEP3203F50 概述. 第2 章 ARM7TDMI 内核第3 章 EMI 外部存储器接口第4 章片上SRAM 第5 章时钟与功耗管理模块PMC 第6 章 LCD 控制器第7 章 MMA 多媒体加速器第8 章 DMA 控制器第9 章 INTC 中断控制器. 第10 章 RTC 实时时钟控制器. 第11 章 TIMER 通用定时器第12 章 UART 通用异步收发器. 第13 章 SPI 串行外设接口第14 章 USB 设备接口第15 章 PWM 脉冲调制器. 第16 章多媒体卡控制器MMC/SD 第17 章 AC 97 控制器第18 章 GPIO 通用输入输出.-East Core IVSEP3203F50 mobile terminal application processor User Manual Chapter 1 outlines the East Core IV SEP3203F50. Chapter 2 ARM7TDMI cores Chapter 3 EMI External Memory Interface Chapter 4 on-chip SRAM Chapter 5 clock and power management module PMC Chapter 6 LCD Controller Chapter 7 MMA Multimedia Accelerator Chapter 8 DMA Controller Chapter 9 INTC interrupt controller. Chapter 10 RTC real time clock controller. Chapter 11 General TIMER timer Chapter 12 UART Universal Asynchronous Receiver Transmitter. No. Chapter 13 SPI Serial Peripheral Interface Chapter 14 USB Device Interface Chapter 15 PWM pulse modulator. Chapter 16 Multimedia Card controller MMC/SD Chapter 17 AC 97 controller Chapter 18 GPIO General Purpose Input Output.
Update : 2025-02-17 Size : 1.74mb Publisher : zk
[VHDL-FPGA-Verilog] SRAM_16Bit_512K DL : 0: Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Update : 2025-02-17 Size : 11kb Publisher : zhyy
[Embeded-SCM Develop] CA9260 DL : 0: 带Java扩展的ARM926EJ-S内核, 2 x 8KB快取, MMU 2x4k Bytes SRAM, 32kBytes Boot ROM 210MHz, 230MIPs EBI –可支持SDRAM, NAND Flash (带ECC)和Compact Flash USB控制器和USB器件口, V2.0全速 Ethernet MAC - 10/100 图像传感器界面 (CMOS传感器界面) 1 SSC可支持I2S和TDM 2 SPI, MCI (SDCard和MMC兼容), TWI 6 USARTs, 支持IrDA, ISO7816 T=0/T=1, RS485-Java extension with ARM926EJ-S core, 2 x 8KB cache, MMU2x4k Bytes SRAM, 32kBytes Boot ROM210MHz, 230MIPsEBI- can support SDRAM, NAND Flash (with ECC) and Compact FlashUSB controller and the USB device port, V2.0 full speed Ethernet MAC- 10/100 Image Sensor Interface (CMOS sensor interface) 1 SSC can support I2S and TDM2 SPI, MCI (SDCard and MMC compatible), TWI6 USARTs, support for IrDA, ISO7816 T = 0/T = 1, RS485
Update : 2025-02-17 Size : 2.36mb Publisher : xujj
[SCM] SRAM DL : 0: F020集成以太网接口核心模块SRAM例程源代码-F020 integrated Ethernet interface module SRAM core routine source code
Update : 2025-02-17 Size : 113kb Publisher : yang
[Embeded-SCM Develop] sls_sram_16_bit DL : 0: altera NIOS软核系统中构建外接SRAM接口的例子-altera NIOS soft-core system to build external SRAM interface example
Update : 2025-02-17 Size : 3kb Publisher : 黄杰
[VHDL-FPGA-Verilog] DE2_NIOS_LITE_SRAM DL : 0: DE2-SRAM-IP-CORE 需要开发ip core的朋友可以参考哦 ~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
Update : 2025-02-17 Size : 1.5mb Publisher : 张曦
[Other] CS8955TV_source_code DL : 0: CS8955控制TV软件。用MCU做模拟电视的控制。-CS8955+TV+TNJ7355(tuner).The CS8955 micro-controller is an 8051 CPU core embedded device targeted for LCD Monitor, LCD TV, Home Appliance, or Consumer Products application. The CS8955 is pin-out compatible with MCS-51 family .MCU. It includes an 8051 CPU core, a 64K-byte internal program Flash-ROM, a 512-byte SRAM, 6 channels of PWM DAC, and 4 channels of 6-bit ADC (Analog to Digital Converter). It also includes a Boot- Code-Free ISP (In System Programming), which allows users to update the programming codes easily. In addition, there are two IIC Slave B ports supporting VESA DDC 2B/2Bi/2B+/CI standards for both D-sub and DVI interfaces in LCD Monitor/TV application. An external 64K bytes data flash memory can be accessed by properly setting of Port 0, Port 2 and Port 3.6/3.7.
Update : 2025-02-17 Size : 565kb Publisher : martinliao
[VHDL-FPGA-Verilog] SRAM_Controller DL : 0: Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
Update : 2025-02-17 Size : 317kb Publisher : vicky
[VHDL-FPGA-Verilog] Sram_core DL : 0: Implementation a Sram Controller Core
Update : 2025-02-17 Size : 170kb Publisher : Khoa
[MiddleWare] foad_cap_sensor_CODEVISION_SOURCE DL : 0: Chip type : ATmega16 Program type : Application Clock frequency : 16.000000 MHz Memory model : Small Optimize for : Size (s)printf features : int, width (s)scanf features : int, width External SRAM size : 0 Data Stack size : 256 byte(s) Heap size : 0 byte(s) Promote char to int : No char is unsigned : Yes 8 bit enums : Yes Word align FLASH struct: Yes Enhanced core instructions : On Automatic register allocation : On- Chip type : ATmega16 Program type : Application Clock frequency : 16.000000 MHz Memory model : Small Optimize for : Size (s)printf features : int, width (s)scanf features : int, width External SRAM size : 0 Data Stack size : 256 byte(s) Heap size : 0 byte(s) Promote char to int : No char is unsigned : Yes 8 bit enums : Yes Word align FLASH struct: Yes Enhanced core instructions : On Automatic register allocation : On
Update : 2025-02-17 Size : 39kb Publisher : mahaseni
[Embeded-SCM Develop] MCU_Design_traffic_lights DL : 0: 本次设计为十字路口交通灯控制系统设计,硬件部分它以8031单片机为核心,并在此基础上扩展了程序存储器（EPROM）2764、静态数据存储器（SRAM）6264，利用地址锁存器74LS373扩展I/O并行接口芯片8255A。软件部分它结合定时/计数等知识进行程序编译。-The design for the intersection traffic light control system design, hardware components it to 8031 as the core, and on this basis, expanded program memory (EPROM) 2764, static data memory (SRAM) 6264, extended use of address latch 74LS373 I/O parallel interface chip 8255A. It combines the software part of the timer/counter and other knowledge to compile.
Update : 2025-02-17 Size : 42kb Publisher : jk
[SCM] LPC1766 DL : 0: 32-bit ARM Cortex-M3 microcontroller up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN-The LPC1768/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
Update : 2025-02-17 Size : 218kb Publisher : 王广龙
[VHDL-FPGA-Verilog] mb_support_sram DL : 0: 配置MB软核使其支持，SRAM并在此基础上做UART测试，文章（我写的呵呵）详细的讲了如何从最对SRAM时序进行配置，如何设置相应参数，如何生成硬件平台，实在是入门必备。-configure the MB ip core to support SRAM .and ,do a test with dsp uart
Update : 2025-02-17 Size : 350kb Publisher : hound
[ARM-PowerPC-ColdFire-MIPS] STM3210ELK DL : 0: STM3210E-LK 开发板的使用手册 -User manual of STM3210E-LK learning kit The STM3210E-LK is a version of the STM32-LK learning kit for the STM32F103ZET6 (LQFP144) microcontroller. The STM32F103ZET6 is high density STM32 microcontroller based on the Cortex-M3 core, with 512 Kbytes of embedded Flash memory and a rich set of on-chip peripherals. The STM3210E-LK learning kit has an embedded ST-LINK JTAG emulator allowing it to be used as an evaluation and demonstration board with all required functions for: ●Emulation ●Debugging ● Flash programming Interfaces and peripherals provided are: USB, CAN, USART, LCD, ADC, SRAM, NOR Flash, NAND Flash, input keys and joystick.
Update : 2025-02-17 Size : 458kb Publisher : zhiyongzi
[VHDL-FPGA-Verilog] VGA_CCD531 DL : 0: 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的转换与显示等功能，并能通过键盘操作和用户界面控制样机拍照和相片浏览。实验结果表明本样机系统设计正确，软硬件各模块绝大部分工作正常，为进一步研究数码相机的应用建立起了一个实用平台。-This paper focuses on a Nios II soft core processors, programmable on-chip system to launch a digital camera prototype design. Firstly, the overall function of the prototype to be achieved by planning, then in parallel hardware and software design. Take full advantage of the hardware side, using the platform provided by the SD card slot, keyboard, digital tube, SRAM and other hardware resources, and using Verilog HDL hardware description language to design a prototype system VGA interface controller, CMOS image sensors interface controller and the VGA display memory the software side, based on the Nios II soft core processor implemented in C, the SD card driver, and the transplantation of the FAT file system, the VGA display driver, and BMP image file conversion and display function, and through the keyboard and user interface control prototype photographs and photo browsing. The experimental results show that this prototype system is designed properly, most of the hardware and softwa
Update : 2025-02-17 Size : 14.38mb Publisher :
[VHDL-FPGA-Verilog] SRAM DL : 0: 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
Update : 2025-02-17 Size : 9kb Publisher : 于洋
[VHDL-FPGA-Verilog] 异步FIFO DL : 1: 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
Update : 2025-02-17 Size : 2kb Publisher : wt2110

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