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[VHDL-FPGA-Verilog] sram__

Description: 静态随机读取存储器行为模型，可以应用于modelsim环境的仿真。-static random acts of reading memory model can be applied to the simulation environment modelsim.
Platform: | Size: 2048 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] IS64LV6416L

Description: Asynchronous SRAM IS64LV6416L modelsim仿真模型-Asynchronous SRAM IS64LV6416L Verilog model
Platform: | Size: 24576 | Author: veriyc | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it is read and write for IS61LV24516 model, if not required for this type of SRAM timing of the program changes. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 1024 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 用Verilog实现8051sdam，并在Quartus和modelsim上完成测试和仿真，内含源代码和测试程序。-Using Verilog realize 8051sdam, and complete testing and simulation, including source code and test procedures in Quartus and modelsim.
Platform: | Size: 1176576 | Author: Lillian | Hits:

[hardware design] 添加库2

Description: 在modelsim中实现硬件库的调用，实现类似SRAM的仿真(Implement the call of the hardware Library in Modelsim and implement the simulation like SRAM)
Platform: | Size: 2276352 | Author: 雾部17 | Hits:

[SCM] eda

Description: 在Verilog HDL中使用任务（task）， 利用有限状态机进行时序逻辑的设计，利用SRAM设计一个LIFO(In Verilog HDL, the task (task) is used, the finite state machine is used to design the time series logic, and a LIFO is designed by SRAM)
Platform: | Size: 3072 | Author: 随风sf | Hits:

[VHDL-FPGA-Verilog] HEX2MIF

Description: QUARTUS II SRAM/ROM初始化需要的HEX文件与Keil产生的HEX格式不同；该Modelsim程序，将Keil产生的Hex转换成，Quartus可以是识别的MIF格式；(The QUARTUS II SRAM/ROM initialization needs HEX files which are different from those generated by Keil. The Modelsim program converts Hex generated by Keil to Quartus, which can be recognized as the MIF format.)
Platform: | Size: 1024 | Author: MCUMaster | Hits:

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