Search - SYSGEN

[OS program] YC2440_bsp

Description: 第一次编译，选择Build and Sysgen，并且确认Clean Before Building 选上。Copy Files to Release Directory After Build h和Make Run-Time Image After Build是指Build结束后，自动拷贝到下，自动生成镜像文件Xip.nb0。如Build时未选上，则可以分别执行下面的两个同名的菜单项来完成。
Platform: | Size: 2966778 | Author: 野猪 | Hits:

[OS program] YC2440_bsp

Description: 第一次编译，选择Build and Sysgen，并且确认Clean Before Building 选上。Copy Files to Release Directory After Build h和Make Run-Time Image After Build是指Build结束后，自动拷贝到下，自动生成镜像文件Xip.nb0。如Build时未选上，则可以分别执行下面的两个同名的菜单项来完成。-The first compiler, select Build and Sysgen, and to confirm the Clean Before Building elected. Copy Files to Release Directory After Build h and Make Run-Time Image After Build after Build means to automatically copy to the next, automatically generated image file Xip.nb0. If the Build is not selected, you can perform the following two, respectively, of the same name of the menu items to complete.
Platform: | Size: 2966528 | Author: 野猪 | Hits:

[Wavelet] conv5x5_matlab_jtag_XUP_hw_in_loop

Description: Xilinx MATLAB、SysGen的图像 DCT工程-Xilinx MATLAB, SysGen image DCT works
Platform: | Size: 72704 | Author: xiaowei | Hits:

[Modem program] SysgenQAM16Demodulation

Description: 采用Xilinx的Sysgen工具建立的16QAM调制解调模型，其中包括信源生成、多普勒频偏、载波跟踪环路等。-Established by the use of Simulink model of 16QAM modulation and demodulation, including source generation, Doppler shift, such as carrier tracking loop.
Platform: | Size: 29696 | Author: brady.zhou | Hits:

[Windows Develop] sysgen

Description: Binary data generator
Platform: | Size: 3072 | Author: ali | Hits:

[Other] henon

Description: chaotic generator of henon by xilinx sysgen and simulink
Platform: | Size: 13312 | Author: merahlah | Hits:

[VHDL-FPGA-Verilog] mail2xilinx

Description: sysgen example for FFT application
Platform: | Size: 1176576 | Author: bala | Hits:

[Windows CE] WinCE_Driver3

Description: 为什么WINCE目录下的例子用build+sysgen能够编译成EXE文件，而我添加的例子就不能编译呢？如果这个例子是一个应用程序，那么肯定包括代码文件（.h .c .cpp）和资源文件（.rc和其它资源文件），build工具根据source文件内容把代码文件编译成lib文件，资源文件编译成.res文件，sysgen工具根据makefile文件内容将source文件中列出的需要链接的各个库文件合并成一个EXE文件。所以说关键在于makefile文件，WINCE目录下凡是能够用-Why WINCE directory example of using the build+ sysgen able to compile into EXE files, and I can not compile the example to add it? If this example is an application, it must include the code file (. H. C. Cpp) and the resource file (. Rc and other resource files), build tools based on source code files to compile the contents of the file into a lib file, resource file is compiled into. res files, sysgen tool according to the makefile file contents will be listed in the source files need to link the various library files into one EXE file. So the key is makefile file, WINCE directory of those who can use
Platform: | Size: 12288 | Author: chenl | Hits:

[matlab] systemgen_mpeg

Description: 平台（Matlab2008a，Simulink，Sysgen 10.1.03）硬件实现RGB2YCbCr -Platform (Matlab2008a, Simulink, Sysgen 10.1.03) hardware realise of RGB2YCbCr
Platform: | Size: 97280 | Author: 翠 | Hits:

[VHDL-FPGA-Verilog] con_inr

Description: 在simulink下用sysgen的基本IP核搭建并实现卷积交织的功能，仿真结果正确，修改参数后可以改变不同的结构。-to implent a convolution-interleaver ,the paramater can change
Platform: | Size: 23552 | Author: 杜飞飞 | Hits:

[Windows Develop] TSysgenQAM16Dh

Description: 采用Xilinx的Sysgen工具建立的16QAM调制制解调模型，其中包括信源生成、多普勒频偏、载波跟踪环路等。 -16QAM modulation using Xilinx Sysgen tool to establish the modem model, including source to generate the Doppler shift, the carrier tracking loop.
Platform: | Size: 29696 | Author: 防止 | Hits:

[VHDL-FPGA-Verilog] dac_adc

Description: vhdl dac_adc.mdl its sysgen model file for xilinx platform
Platform: | Size: 14336 | Author: sanjeev | Hits:

[Other] DSP-SYSGEN

Description: Design of system using DSP System Generator
Platform: | Size: 3145728 | Author: Mayank Srivastava | Hits:

[DSP program] sysgen-labs

Description: xilinx 公司DSP培训实验PDF文档；-xilinx company DSP training experiment PDF documents
Platform: | Size: 1311744 | Author: 闵文斌 | Hits:

[VHDL-FPGA-Verilog] evodem_mppt_son_hali_OK

Description: This my complete simulink project using xilinx system generator blocks. There is a buck converter and a control unit for FPGA calculating MPPT to get maximum power from the PV panel. MPPT calculation is done using sysgen blocks. Also HWCOSIM (hardware cosim is done and the files are present bit file etc...) Enjoy. :)-This is my complete simulink project using xilinx system generator blocks. There is a buck converter and a control unit for FPGA calculating MPPT to get maximum power from the PV panel. MPPT calculation is done using sysgen blocks. Also HWCOSIM (hardware cosim is done and the files are present bit file etc...) Enjoy. :)
Platform: | Size: 2967552 | Author: onur | Hits:

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[OS program] YC2440_bsp

[OS program] YC2440_bsp

[Wavelet] conv5x5_matlab_jtag_XUP_hw_in_loop

[Modem program] SysgenQAM16Demodulation

[Windows Develop] sysgen

[Other] henon

[VHDL-FPGA-Verilog] mail2xilinx

[Windows CE] WinCE_Driver3

[matlab] systemgen_mpeg

[VHDL-FPGA-Verilog] con_inr

[Windows Develop] TSysgenQAM16Dh

[VHDL-FPGA-Verilog] dac_adc

[Other] DSP-SYSGEN

[DSP program] sysgen-labs

[VHDL-FPGA-Verilog] evodem_mppt_son_hali_OK

[Other] 1-SysgenIntro_Part1

[Other] 1-SysgenIntro_Part2

[Other] Computer Vision with SG

[Other] Image_Filter_SystemGen_Tut

[Other] Video Encryption System with SG

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