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[Other resource] scaler

Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。
Platform: | Size: 9734 | Author: wgy | Hits:

[VHDL-FPGA-Verilog] scaler

Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Platform: | Size: 9216 | Author: wgy | Hits:

[VHDL-FPGA-Verilog] jishuqi

Description: 使用VHDL语言实现计数器功能 ……使用VHDL语言实现计数器功能 -Use VHDL language scaler functions……Use VHDL language scaler functions
Platform: | Size: 87040 | Author: 潘燕萍 | Hits:

[VHDL-FPGA-Verilog] video

Description:
Platform: | Size: 3486720 | Author: liao | Hits:

[Industry research] ds840_v_scaler

Description: v scaler xilinx vhdl
Platform: | Size: 1308672 | Author: david | Hits:

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