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[Com Portserial_null

Description: SUDT SerialNull 是一款虚拟串口的专业配置工具,主要用于模拟RS232串口的虚拟连接,适用于串行口相关的软硬件开发、测试工程师。在系统中所创建的虚拟串口在功能以及使用上与真实物理串口一致。可以在不占用真实串口的情况下,创建任意数量并互为连接的纯虚拟串口对。 -SUDT SerialNull is a virtual serial port configuration of the major instrument, mainly used to simulate a virtual RS232 serial port connection, applied to the serial port hardware and software related to development, testing engineers. In the system by creating virtual serial port in the functional and the use of on with the real physical serial line. Can not occupy the real serial circumstances, and each other to create any number of pure virtual serial port to connect right.
Platform: | Size: 564224 | Author: yu | Hits:

[SCMNUC140_CAN_Master_CoOS

Description: 设备: Nuvoton NUC140VE3AN 评估板: Nu-LB_002 Rev2.0 编译器: CoIDE V1.1.0 任务: task_init 初始化目标板的资源,并创建其它任务,然后自我删除并退出调度。 get_datab 根据从子机接收到的ID数据,获得该ID的数据库信息。 update_db 等待输入消费金额,然后通过CAN发送消费金额到主机。 uart_print 打印余额。 描述: 本例子模拟了一个打卡消费系统的子机。在测试时,需要和一个打卡消费系统的主机对接: 1. 利用串口输入模拟打卡动作,利用AD输入模拟消费金额的输入动作。 2. 和主机通讯成功后,子机会显示此时插入卡的余额、消费状态和消费后余额。 系统配置: 时钟设置: XTAL freq = 12.00 MHz SYSCLK freq = 12.00 MHz System Tick freq = 100Hz (10ms)-Equipment: Nuvoton NUC140VE3AN evaluation board: Nu-LB_002 Rev2.0 compiler: CoIDE V1.1.0 task: task_init initialize the target board resources, and create other tasks, and then self-delete and exit scheduling. get_datab according to the ID of the data received from the sub-machine, access to the ID database information. update_db waiting for input the amount of consumption, the consumption amount to the host and then be sent via CAN. uart_print Print balance. Description: This example simulates a punch card consumer' s handset. Test and the butt of a punch card the consumption system' s host: 1 serial input analog punch action, take advantage of the AD the input analog spend the input action. 2 and host communication is successful, the child the opportunity to insert the card balance, consumption status and post-consumer balance. System configuration: clock settings: XTAL freq = 12.00 MHz SYSCLK freq = 12.00 MHz System Tick freq = 100Hz (10ms)
Platform: | Size: 197632 | Author: peter | Hits:

[VHDL-FPGA-Verilogchuankoushoufa

Description: 接收代码: 对接收数据的采样频率:16X9600HZ 接收代码编写思路: 首先判断起始位,没有数据传输时,起始位为“1”的状态,当有数据时起始位为“0”。因为采样的频率是通信频率的16倍,所以当连续8次(数据位正中间)采集为“0”时就认为是有数据到来。那么可以开始采集数据位,以后每隔16个脉冲采集一个数据(每个数据的正中央,不易发生畸变的部分),连续采样8次,即完成数据位的采集。最后实现串并转换。如此重复即可。(因为通信已经预约好,停止位和校验位都为“1”,不会对数据产生影响。) 发送端代码编写思路: 先判断发送闲忙,如果发送的线路空闲,便可以读入数据,读入时就对数据加起始位“0”。因为数据是并行输入的,必须按位去取,形成串行数据,这时的数据位数变为9位,再给这些数据加上校验位“1”和停止位“1”即可。最后11位数据按位输出。完成发送。 程序部分也有一定说明或注释. -Receive code: Sampling frequency of the received data: 16X9600HZ Receive coding ideas: Analyzing first start bit, the start bit is "1" state when no data is transmitted, when the data start bit is "0". Because the sampling frequency is 16 times the communication frequency, so that it is collected eight consecutive times (data bit is in the middle) to "0" when data soon. Can begin collecting data bits, a collection of data (the middle of each data after every 16 pulses, less prone to distortion of the part), 8 consecutive samples, i.e. to complete the acquisition of the data bit. Finally realize the serial-to-parallel conversion. So can be repeated. (Because the communication has an appointment, stop bits and parity bits are "1", the data will not have an impact.) Sender coding ideas: First determine Send Free Busy, if the transmission line is idle, you can read the data read in the data start bit "0". Because the data is parallel input, serial data bit and get to form, when the nu
Platform: | Size: 86016 | Author: ran feng | Hits:

[Othergao_gg25

Description: Simulation of the effect is very good, Use serial programming examples matlab GUI implementation, Phased array antenna pattern (Chebyshev weights).
Platform: | Size: 39936 | Author: 雷瑞科雷瑞科 | Hits:

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