Search - Simulink System Generator

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[VHDL-FPGA-Verilog] simulink-03-31 DL : 0: 基于MATLAB/DSP Ｂuild可控信号发生器，由Ｍatlab建模综合，并生成ＶＨＤＬ代码，由Ｑuartus编译通过．-Based on MATLAB/DSP Build controllable signal generator, by the Matlab modeling synthesis, and generates VHDL code, adopted by the Quartus compiler.
Update : 2025-02-19 Size : 291kb Publisher : ltianyang
[matlab] Application_in_FPGA_design_of_Matlab_simulink DL : 0: 分析了MATLAB/Simulink 中DSP Builder 模块库在FPGA 设计中优点，然后结合FSK 信号的产生原理，给出了如何利用DSP Builder 模块库建立FSK 信号发生器模型，以及对FSK 信号发生器模型进行算法级仿真和生成VHDL 语言的方法，并在modelsim 中对FSK 信号发生器进行RTL 级仿真，最后介绍了在FPGA 芯片中实现FSK 信号发生器的设计方法。-Analysis of the MATLAB/Simulink in DSP Builder Blockset in the FPGA design advantages, and then combined with the emergence of the principle of FSK signal is given how to use DSP Builder Blockset establish FSK signal generator model, as well as the FSK signal generator model algorithm class VHDL simulation and generation language approach, and in ModelSim for FSK signal generator for RTL-level simulation, and finally introduce the FPGA chip realize FSK signal generator design method.
Update : 2025-02-19 Size : 269kb Publisher : 普林斯
[matlab] sysgen_gs DL : 0: Xilinx system generator的上手指南，system generator用于在matlab中使用simulink设计硬件，很方便-guide of system generater by Xilinx
Update : 2025-02-19 Size : 1.61mb Publisher : 王静
[VHDL-FPGA-Verilog] lab1 DL : 0: system generator/simulink 应用开发实例，User Starting
Update : 2025-02-19 Size : 151kb Publisher : troy
[matlab] lab2 DL : 0: system generator/simulink 应用开发2，User Starting
Update : 2025-02-19 Size : 154kb Publisher : troy
[VHDL-FPGA-Verilog] lab4 DL : 0: system generator/simulink 应用开发4，User Starting
Update : 2025-02-19 Size : 118kb Publisher : troy
[matlab] lab5 DL : 0: system generator/simulink 程序联合开发5 get starting
Update : 2025-02-19 Size : 253kb Publisher : troy
[File Format] Simulink-Model-of-Seig DL : 0: Dynamic and steady state model of Doubly fed induction generator back to back supply for wind energy power system using matlab
Update : 2025-02-19 Size : 359kb Publisher : mohammad
[DSP program] OFDM_Security DL : 0: This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA. The RAR file inlcudes 2 files: 1. Simulink model 2. initialization file. Software requirements: 1. Matlab, r2007a or later 2. Simulink with DSP and Comm blocksets 3. Xilinx ISE with System Generator for DSP 9.2i or later.
Update : 2025-02-19 Size : 157kb Publisher : 徐滨
[matlab] simulink-QPSK DL : 0: 对QPSK解调系统完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。 matlab版本：2007a-Perfect for QPSK demodulation system modeling, which by changing the symbol rate and carrier frequency, and then calculate the corresponding parameters of the loop filter, QPSK demodulator can achieve a variety of models, and the model can be quantified by SYSTEM generator thereby generating ISE HDL code can be used directly. matlab version: 2007a
Update : 2025-02-19 Size : 19kb Publisher : 61408520
[matlab] simulink-8PSK DL : 0: 对8PSK完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。-Perfect modeling of 8PSK, wherein by changing the symbol rate and carrier frequency, and calculate the corresponding parameters of the loop filter, to achieve a variety of demodulated QPSK model, and the model can be quantified by SYSTEM generator, thereby generating ISE HDL code can be used directly.
Update : 2025-02-19 Size : 23kb Publisher : 61408520
[SCM] FPGA-design-and-verification-using-Simulink DL : 0: Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ability to functionally simulate a design and use the MATLAB environment to verify bit- and cycle-true models against the golden reference results. These reference results can be produced either externally or inside the MATLAB environment, and you can target a Xilinx FPGA hardware platform all within MATLAB. System Generator complements HDL design tasks by providing an easily configured test bench for both functional-Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ability to functionally simulate a design and use the MATLAB environment to verify bit- and cycle-true models against the golden reference results. These reference results can be produced either externally or inside the MATLAB environment, and you can target a Xilinx FPGA hardware platform all within MATLAB. System Generator complements HDL design tasks by providing an easily configured test bench for both functional
Update : 2025-02-19 Size : 134kb Publisher : jayaprada
[matlab] Smoothing DL : 0: Xilinx System Generator : Smoothing
Update : 2025-02-19 Size : 47kb Publisher : ossang
[Documents] lab1 DL : 0: labs of system generator lab 1:Using Simulink Lab
Update : 2025-02-19 Size : 181kb Publisher : mohsaber
[matlab] Lab2 DL : 0: Lab2 for system generator from xilinx
Update : 2025-02-19 Size : 228kb Publisher : bilalo
[matlab] Lab1_1.slx DL : 0: TP lab1 system generator
Update : 2025-02-19 Size : 28kb Publisher : bilalo
[matlab] Lab1_2.slx DL : 0: TP lab2 system generator
Update : 2025-02-19 Size : 33kb Publisher : bilalo
[matlab] Lab1_3.slx DL : 0: TP lab3 system generator
Update : 2025-02-19 Size : 40kb Publisher : bilalo
[matlab] Lab1_4_1.slx DL : 0: TP lab4 system generator
Update : 2025-02-19 Size : 32kb Publisher : bilalo
[matlab] Solution DL : 0: solution for TP lab1 system generator
Update : 2025-02-19 Size : 192kb Publisher : bilalo

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