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[ARM-PowerPC-ColdFire-MIPS] Spartan3EHDL DL : 0: xlinix 公司的 SPARTAN-3 片子 Spartan-3E HDL 设计库指南本人正在使用如果需要其他信息的可以和我联系-xlinix the SPARTAN-3 film Spartan-3E HDL design library guidelines are in use if I need other information can contact me and
Update : 2025-02-17 Size : 740kb Publisher : 宫城
[VHDL-FPGA-Verilog] S3Demo DL : 0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Update : 2025-02-17 Size : 714kb Publisher : Roy Hsu
[VHDL-FPGA-Verilog] KCPSM3 DL : 0: This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devices by Picoblaze -This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devicesby Picoblaze
Update : 2025-02-17 Size : 1.44mb Publisher : 王斯弘
[VHDL-FPGA-Verilog] left_right_leds DL : 0: 利用Spartan-3 Starter Board实验板上的旋转开关，设计一个通过旋转开关的方向来控制LED灯的依次点亮顺序的实验，并且要求可以循环点亮。-Using Spartan-3 Starter Board experiment on-board rotary switch, the design of a direction through the rotary switch to control the LED lights light up sequence followed by the experiment, and asked could be re-lit.
Update : 2025-02-17 Size : 2kb Publisher : minmin
[Software Engineering] SPARTAN-3E DL : 0: SPARTAN-3E的说明文档,详解的描述了SPARTAN-3E的使用方法-SPARTAN-3E description of documents, detailed description of the SPARTAN-3E use
Update : 2025-02-17 Size : 6.89mb Publisher : 富聪
[VHDL-FPGA-Verilog] pong DL : 0: Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.
Update : 2025-02-17 Size : 73kb Publisher : wangfeng
[VHDL-FPGA-Verilog] Rs232sourcecode DL : 0: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Update : 2025-02-17 Size : 5kb Publisher : Ikki
[VHDL-FPGA-Verilog] Avt3S400A_Eval_MB_parallel_flash_v10_1_01 DL : 0: FPGA 并行NOR FLash的操作相关，很实用的，基于Xilinx SPartan-3 -FPGA parallel operation of NOR FLash related, it is practical, based on the Xilinx SPartan-3
Update : 2025-02-17 Size : 13.04mb Publisher : 沈煌辉
[VHDL-FPGA-Verilog] lcd_driver_4bit DL : 0: it is a 4-bit lcd driver written in verilog .it will work on spartan 3 xilini devices.
Update : 2025-02-17 Size : 3kb Publisher : ali
[VHDL-FPGA-Verilog] Spartan-3E DL : 0: Spartan-3E 中文介绍（包括图解、功能介绍、使用方法、锁管脚等）-Spartan-3E Starter Kit Board User Guide
Update : 2025-02-17 Size : 9.03mb Publisher : weishangqing
[VHDL-FPGA-Verilog] Spartan-3_NeuralNetwork_3-layer_feedforward_backp DL : 0: The aim of this project is the design and implementation of a system simulating a NN in the Spartan-3 Starter Board of Xilinx. The NN will be a 3-layer feedforward backpropagation.- The aim of this project is the design and implementation of a system simulating a NN in the Spartan-3 Starter Board of Xilinx. The NN will be a 3-layer feedforward backpropagation.
Update : 2025-02-17 Size : 1.41mb Publisher : duzos
[VHDL-FPGA-Verilog] rafal2 DL : 0: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Update : 2025-02-17 Size : 919kb Publisher : nukom
[VHDL-FPGA-Verilog] wtut_sc DL : 0: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other.
Update : 2025-02-17 Size : 104kb Publisher : shad
[VHDL-FPGA-Verilog] EDK_81 DL : 0: 视频文件 EDK_81,xilinx spartan-3-EDK_81,xilinx spartan-3
Update : 2025-02-17 Size : 10.35mb Publisher : zhouni
[Linux-Unix] sl361_board_files DL : 0: spartan-3开发板原理图，好东西大家共享-spartan-3 development board schematics, share good things
Update : 2025-02-17 Size : 16.28mb Publisher : 李乔
[GUI Develop] SP305-Spartan-3 DL : 0: SP305 Spartan-3 Development Platform User Guide
Update : 2025-02-17 Size : 719kb Publisher : Alex
[VHDL-FPGA-Verilog] Spartan-3-FPGA-Family-Data-Sheet DL : 0: Spartan-3 FPGA Family Data Sheet
Update : 2025-02-17 Size : 1.84mb Publisher : zdm
[File Format] Spartan-3-Complete-data-sheet DL : 0: Spartan-3 Complete data sheet
Update : 2025-02-17 Size : 1.48mb Publisher : wjk
[File Format] Spartan-3-FPGA-FamilyPinout-Descriptions-data DL : 0: Spartan-3 FPGA FamilyPinout Descriptions data
Update : 2025-02-17 Size : 871kb Publisher : wjk
[VHDL-FPGA-Verilog] ug331 Spartan-3 系列 FPGA 中文用户指南 DL : 0: 官方手册ug331的中文版本用户指南为客户使用 Spartan?-3 FPGA 系列各平台（Spartan-3、Spartan-3E、 Spartan-3A、Spartan-3AN 和 Spartan-3A DSP FPGA 平台）的架构功能提供指导。本文综合了各平台的技术文档，以便于了解其中异同，同时减少多种资料来源的内容重复。这些平台是新设计的补充解决方案。(ug331 Spartan-3 Generation FPGA User Guide)
Update : 2025-02-17 Size : 5.92mb Publisher : xtp1230

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