Search - Spartan-3E VERILOG

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[VHDL-FPGA-Verilog] verilog实现ALU的源代码 DL : 0: verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
Update : 2025-02-17 Size : 1kb Publisher : 飞扬
[VHDL-FPGA-Verilog] VGAVGA DL : 0: 利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序-Verilog prepared using the SPARTAN-based XILINX board VGA Interface display program
Update : 2025-02-17 Size : 2mb Publisher : leestar
[VHDL-FPGA-Verilog] lcd12864 DL : 0: LCD12864 在Spartan-3E实现教程和代码-LCD12864 in the Spartan-3E achieve tutorials and code
Update : 2025-02-17 Size : 981kb Publisher : hushengquan
[VHDL-FPGA-Verilog] ddr2sdram_spartan3s700an.tar DL : 0: It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit- Diligent fully working.
Update : 2025-02-17 Size : 1.42mb Publisher : under
[VHDL-FPGA-Verilog] pong DL : 0: Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.
Update : 2025-02-17 Size : 73kb Publisher : wangfeng
[VHDL-FPGA-Verilog] lcd_driver_4bit DL : 0: it is a 4-bit lcd driver written in verilog .it will work on spartan 3 xilini devices.
Update : 2025-02-17 Size : 3kb Publisher : ali
[VHDL-FPGA-Verilog] spartan_alu_8_bit DL : 0: Verilog based 8 bit ALU module, implemented on Spartan 3E FPGA.
Update : 2025-02-17 Size : 9kb Publisher : ifusmell
[VHDL-FPGA-Verilog] stopwatch DL : 0: The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
Update : 2025-02-17 Size : 2kb Publisher : flyingwings
[VHDL-FPGA-Verilog] DDS_FINAL DL : 0: My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency. We can change the frequency using frequency selector input. Please accept this project. We use the SPARTAN 3E 500 device to implement it.
Update : 2025-02-17 Size : 427kb Publisher : Raju Kumar
[VHDL-FPGA-Verilog] Vga DL : 0: The code is used to interface PC monitor with Spartan 3E for the display. if you run the program on spartan 3 you would be able to see different test pattern on the monitor screen
Update : 2025-02-17 Size : 612kb Publisher : asit
[VHDL-FPGA-Verilog] c_xapp454 DL : 0: 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and the Micron DDR2 SDRAM device is connected, Spartan ™ -3 devices DDR2 SDRAM memory interface implementation. This document briefly describes the DDR2 SDRAM device features, and then the realization of DDR2 SDRAM memory interface is described in detail.
Update : 2025-02-17 Size : 212kb Publisher : 陈阳
[Other Embeded program] msblsb_seperation DL : 0: This program seperates MSB and LSB of a two digit number in verilog and implemented on SPARTAN 3E.
Update : 2025-02-17 Size : 278kb Publisher : kal
[VHDL-FPGA-Verilog] adc2 DL : 0: ADC control in VHDL language. Spartan 3E starter pack ISE 10.1
Update : 2025-02-17 Size : 199kb Publisher : khoosram
[VHDL-FPGA-Verilog] led_rotary DL : 0: Spartan-3E实验板，基于Verilog实现旋转按钮控制八个LED灯移动方向。- a program by verilog that can control the leds in the spartan-3e lights direction by the rotary button on it.
Update : 2025-02-17 Size : 292kb Publisher : 陈海凯
[VHDL-FPGA-Verilog] lcd_test DL : 0: Xilinx Spartan-3E实验板上基于verilog控制lcd屏幕A到Z反复轮转显示。-Xilinx Spartan-3E verilog based test control board lcd screen A to Z repeated rotary display.
Update : 2025-02-17 Size : 976kb Publisher : 陈海凯
[VHDL-FPGA-Verilog] IS61WV51216BLL DL : 0: 备注：使用的是VeriLog HDL语言软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher Miriam EXCD-1FPGA circuit boards. FPGA Signal: spartan-3e. Write functional hardware description language implementation of on-board peripherals SRAM IS61WV51216BLL FPGA to read and write, sent to the host computer through the serial port, use the serial Assistant displays the data read.
Update : 2025-02-17 Size : 5kb Publisher : 李钿
[VHDL-FPGA-Verilog] lcd DL : 0: SPARTAN 3E 开发板驱动程序 Verilog源码对于数字电路设计是很好的参考资料-SPARTAN 3E development board driver for digital circuit design, Verilog source code is a good reference
Update : 2025-02-17 Size : 2kb Publisher : wang
[VHDL-FPGA-Verilog] 1024FFT-verilog-hdl DL : 0: 基于spartan 3e 的IFFT算法verilog HDL程序-Based on the verilog 3e Spartan IFFT algorithm of HDL program
Update : 2025-02-17 Size : 427kb Publisher : caizhixiang
[VHDL-FPGA-Verilog] Xilinx-verilog DL : 0: xilinx培训源码及工程文件,给予spartan 3E开发板的！希望对初学者有所帮助-Xilinx training codes and project！！ IT‘s worth to learn！！
Update : 2025-02-17 Size : 11.39mb Publisher : tao
[Other] pong_game DL : 0: pong game on spartan 3e (verilog)
Update : 2025-02-17 Size : 691kb Publisher : wimiu

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