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[Other resource] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233299 | Author: 杰轩 | Hits:

[Other resource] Designing_with_Quartus

Description: 1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic -1) Learn more about the capabilities in Qua rtus : 2) Learn to use different design entry techniqu es 2) Design entry methods available within Qua rtus Text editor, Block diagram / schematic file editor, Quartus interface with design entry / synthesi s tools from Exemplar, Synopsys. Synplicity and Viewlogic
Platform: | Size: 2713987 | Author: Jawen | Hits:

[Develop Tools] synplicity

Description: 很不错的一本介绍synplicity的书,很值得一看,适合大众类人群
Platform: | Size: 890060 | Author: feng | Hits:

[Other resource] synplicity

Description: synplicity学习资料，文章详细介绍了vhdl在该仿真软件中的仿真过程
Platform: | Size: 834877 | Author: hufeng | Hits:

[Other resource] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段 时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的 大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细 描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。
Platform: | Size: 1945930 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233472 | Author: 杰轩 | Hits:

[Other] Designing_with_Quartus

Description: 1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic -1) Learn more about the capabilities in Qua rtus : 2) Learn to use different design entry techniqu es 2) Design entry methods available within Qua rtus Text editor, Block diagram/schematic file editor, Quartus interface with design entry/synthesi s tools from Exemplar, Synopsys. Synplicity and Viewlogic
Platform: | Size: 2713600 | Author: Jawen | Hits:

[Books] synplicity

Description: 很不错的一本介绍synplicity的书,很值得一看,适合大众类人群-Very good Synplicity introduced a book, it is worth a visit for the general public category of the crowd
Platform: | Size: 889856 | Author: feng | Hits:

[VHDL-FPGA-Verilog] synplicity

Description: synplicity学习资料，文章详细介绍了vhdl在该仿真软件中的仿真过程-Synplicity learning materials, the article introduced in detail in the VHDL simulation software in the simulation process
Platform: | Size: 834560 | Author: hufeng | Hits:

[VHDL-FPGA-Verilog] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段 时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的 大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细 描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Platform: | Size: 1945600 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] Synplify.Premier.v9.6.2.with.Identify.3.0.2

Description: Synplify.Premier.v9.6.2.with.Identify.3.0.2 crack
Platform: | Size: 13312 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] FPGA_NEW_APPROACH_TO_IMPLEMENT_CHAOTIC_GENERATOR.

Description: In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.-In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.
Platform: | Size: 253952 | Author: gsbnd | Hits:

[VHDL-FPGA-Verilog] 1(3)

Description: 确实是 介绍synplicity.的一本好书-synplicity.synplicity.
Platform: | Size: 1010688 | Author: tang | Hits:

[VHDL-FPGA-Verilog] Crash.the.Simulation.Barrier

Description: 确实是 介绍synplicity.的一本好书-synplicity.synplicity.
Platform: | Size: 415744 | Author: tang | Hits:

[VHDL-FPGA-Verilog] synplicity_license_lin_ug

Description: Synplicity Linux License Configuration and Setup Guide，Linux下License配置与环境建立手册，那是相当的不错喔！-Synplicity Linux License Configuration and Setup Guide, Linux configuration and the environment established under the License Manual, which is pretty good Oh!
Platform: | Size: 274432 | Author: Jasking Wu | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[Other] Synplify_T

Description: Synplicity的工具涵盖了可编程逻辑器件的综合，验证，调试，物理综合及原型验证等领域，这是对Synplicity学习很有帮助的一本教材-Synplicity' s tools covers the programmable logic device synthesis, verification, debugging, physical synthesis and prototype verification and other fields, this is very helpful Synplicity' s a textbook
Platform: | Size: 873472 | Author: shen | Hits:

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