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[VHDL-FPGA-Verilog] watch

Description: vhdl语言编写的一个秒表源码，包括在LCD上显示的部分，附带TB源码，对初学者比较实用-VHDL language, a stopwatch source, including the LCD display part, incidental TB source, more practical for beginners
Platform: | Size: 98304 | Author: ronniy | Hits:

[VHDL-FPGA-Verilog] TB_VHDL(adder)

Description: 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
Platform: | Size: 1024 | Author: 帅哥新 | Hits:

[VHDL-FPGA-Verilog] 4613m73a_nand_model

Description: File Descriptions: --- --- --- nand_model.v -structural wrapper for nand_die_model nand_die_model.v -nand model of a single die nand_defines.vh -file used to generate correct port maps for nand_model instanciation. nand_parameters.vh -file that contains all parameters used by the model readme.txt -this file tb.v -nand model test bench tb.do -compiles and runs the nand_model and test bench-File Descriptions: ------------------ nand_model.v -structural wrapper for nand_die_model nand_die_model.v -nand model of a single die nand_defines.vh -file used to generate correct port maps for nand_model instanciation. nand_parameters.vh -file that contains all parameters used by the model readme.txt -this file tb.v -nand model test bench tb.do -compiles and runs the nand_model and test bench
Platform: | Size: 88064 | Author: akjfklaskdfj | Hits:

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[VHDL-FPGA-Verilog] watch

[VHDL-FPGA-Verilog] TB_VHDL(adder)

[VHDL-FPGA-Verilog] 4613m73a_nand_model

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