Search - Tri Mode

[Other resource] LPC900ICPSpecen

Description: When the P89LPC90x is in programming mode all pins that are not used for programming are tri-stated. During programming mode the reset pin has a weak pull-up resistor.-When the programming is in a mode 'll pins that are not used for programming are tri - stated. During programming mode the reset pin has a weak pull-up resistor.
Platform: | Size: 90131 | Author: ansem | Hits:

[SCM] LEDsanjishe

Description: 本文给出基于单片机系统的16×15 三色LED 点阵双显示屏设计方案,采用动态显示原理,配合优化的程序设计,在动态扫描方式下,得到较高刷新速率、画面清晰的三色显示效果。本设计实现了由红、黄、绿组成的十二种颜色搭配的静态和动态字符、文字、动画显示：集成ASCII 码子库显示；四条广告语的十二种颜色循环显示；生动的动画显示。按键控制上下左右移动及速度大小和灰度等级。【关键词】三色LED 显示屏动态显示单片机双-In this paper, based on single-chip microcomputer system of 16 × 15 three-color LED dot-matrix dual-screen design, the use of dynamic display principle, with the optimized programming, in a dynamic scan mode, get a higher refresh rate, frame-accurate three- color display. The design by the red, yellow and green, composed of 12 kinds of colors of the static and dynamic characters, text, animation show: Integrated ASCII different library display four of the 12 kinds of advertisement cycle color display vivid animation show . About moving up and down buttons control the speed and size and gradation. [Key Words] tri-color LED display single-chip dual dynamic display
Platform: | Size: 189440 | Author: www | Hits:

[Software Engineering] LPC900ICPSpecen

Description: When the P89LPC90x is in programming mode all pins that are not used for programming are tri-stated. During programming mode the reset pin has a weak pull-up resistor.-When the programming is in a mode 'll pins that are not used for programming are tri- stated. During programming mode the reset pin has a weak pull-up resistor.
Platform: | Size: 90112 | Author: ansem | Hits:

[Driver Develop] sp487

Description: The SP486 and SP487 are low–power quad differential line drivers meeting RS-485 and RS-422 standards. The SP486 features a common driver enable control the SP487 provides independent driver enable controls for each pair of drivers. Both feature tri–state outputs and wide common–mode input range. Both are available in 16–pin plastic DIP and SOIC packages.-The SP486 and SP487 are low-power quad differential line drivers meeting RS-485 and RS-422standards. The SP486 features a common driver enable control the SP487 provides independentdriver enable controls fo
Platform: | Size: 72704 | Author: yu | Hits:

[File Format] tri_mode_eth_mac_gs_ug139

Description: VIRTEX4中MAC封装,介绍了怎样设置MAC子层,使用它的好处是可以在一个芯片同时实现数据采集和千兆以太网传输-LogiCORE™ Tri-Mode EthernetMAC v3.4
Platform: | Size: 248832 | Author: xj | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode.rel-1-0.tar

Description: ethernet mac verilog code.eth 10 100 1000mb/s
Platform: | Size: 690176 | Author: amir | Hits:

[VHDL-FPGA-Verilog] Tri-mode_Ethernet_MAC_Specifications

Description: document for mac 10 100 1000 ethernet verilog code.you find code in this site
Platform: | Size: 247808 | Author: amir | Hits:

[VHDL-FPGA-Verilog] InterefacingPS2Keyboard

Description: FPGA/keyboard interface is shown in figure 1. When the FPGA “reads” the Data or Clock inputs both PS2Data_out and PS2Clk_out are kept low which puts the tri-state buffers in high impedance mode. When the FPGA "writes" a logic 0 on an output, the corresponding x_out (x = PS2Data or PS2Clk) signal is set high which pulls the line low. When “writing” logic 1 the FPGA simply sets the x_out signal low.
Platform: | Size: 432128 | Author: qweqweqwe | Hits:

[Other] ethernet_tri_mode_latest.tar

Description: 10_100 0 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependance.To increase the flexibility,three optional modules can be added to or removed from the project. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.-10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependance.To increase the flexibility,three optional modules can be added to or removed from the project. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.
Platform: | Size: 3198976 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode

Description: Its an verilog coded ether net tri mode project
Platform: | Size: 3198976 | Author: apranav | Hits:

[Other] MAC_Core

Description: Tri- mode MAC source
Platform: | Size: 471040 | Author: rozenan | Hits:

[Embeded-SCM Develop] Virtex-5EMAC

Description: This application note describes a system using the Virtex™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri-Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.-This application note describes a system using the Virtex ™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri- Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.
Platform: | Size: 492544 | Author: zhang | Hits:

[AI-NN-PR] tri_mode_eth_mac

Description: The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation-The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation
Platform: | Size: 248832 | Author: zhang | Hits:

[ARM-PowerPC-ColdFire-MIPS] xapp957

Description: The system provides an example of how to integrate the Virtex-5 Embedded Tri-Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board and a PC-based Graphical User Interface (GUI) to control the demonstration platform.
Platform: | Size: 3391488 | Author: 田辉 | Hits:

[VHDL-FPGA-Verilog] xapp941

Description: Reference System: PLB Tri-Mode Ethernet MAC
Platform: | Size: 3904512 | Author: fangming | Hits:

[VHDL-FPGA-Verilog] EMAC6

Description: verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.
Platform: | Size: 3602432 | Author: trygov | Hits:

[Internet-Network] Tri-mode_Ethernet_MAC

Description: 此包为三态以太网控制IP核，包内包含了仿真环境，说明文档，综合结果等文件。-This package is tri-mode Ethernet Controller IP core, the package contains a simulation environment, documentation, comprehensive results and other documents.
Platform: | Size: 1158144 | Author: Dongbing | Hits:

[VHDL-FPGA-Verilog] Tri-Eth

Description: 采用xilinx三太以太网ip核，tri-mode MAC完成千兆以太网数据传输-Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed
Platform: | Size: 4827136 | Author: 望天 | Hits:

[Program doc] com5401soft

Description: COM-5401SOFT Tri-Mode 10/100/1000 Ethernet MAC
Platform: | Size: 266240 | Author: prabhakar | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac(LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac)
Platform: | Size: 1024 | Author: liyan2020 | Hits:

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