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[Other resource] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \\ uart source (Verilog) \\ uart source (VHDL) \\ uart16550.tar
Platform: | Size: 295101 | Author: efly | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[Com Port] uart16550

Description: uart source code from opencore
Platform: | Size: 202752 | Author: liuKe | Hits:

[Com Port] uart16550

Description: Ｕａｒｔ　串口的verilog实现已调试通过-verilog　
Platform: | Size: 39936 | Author: wangli | Hits:

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