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[File Format] verilog_testbench_preliminary

Description: verilog testbench preliminary，很有用的-verilog testbench preliminary, very useful
Platform: | Size: 60416 | Author: 刘彦 | Hits:

[VHDL-FPGA-Verilog] I2C_HDL

Description: I2C bus HDL source and testbench
Platform: | Size: 701440 | Author: liuKe | Hits:

[VHDL-FPGA-Verilog] asynch_fifo

Description: FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
Platform: | Size: 1028096 | Author: alison | Hits:

[VHDL-FPGA-Verilog] SPI_FireWall

Description: verilog spi file with testbench
Platform: | Size: 2934784 | Author: xgh | Hits:

[VHDL-FPGA-Verilog] uart_tran

Description: UART串口的传送verilog原程序，已经经过了编译仿真-Verilog UART serial transmission of the original procedure has been compiled after a simulation
Platform: | Size: 269312 | Author: 王迪 | Hits:

[VHDL-FPGA-Verilog] TestBench

Description: 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_logic_vector(v_remd,DWIDTH)) report "ERROR in division!" severity failure
Platform: | Size: 90112 | Author: lei | Hits:

[VHDL-FPGA-Verilog] Springer_2006_SystemVerilog_for_Verificatio_Chris

Description: A Guide to Learning the Testbench System Verilog Language Features
Platform: | Size: 1412096 | Author: aj000 | Hits:

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