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[Other resource] VHDL程序范例

Description: 这是有关VHDL的一些范例，可以通过范例学习一点东西，巩固自己学过的东西-This is the VHDL some examples, examples can learn something consolidate learned things
Platform: | Size: 5085 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] VHDL语言写的音乐演奏程序

Description: 用VHDL语言写的，音乐演奏程序，范例歌曲为“青花瓷”片段。
Platform: | Size: 700184 | Author: xiezheqi | Hits:

[VHDL-FPGA-Verilog] VHDL程序范例

Description: VHDL初级范例
Platform: | Size: 14640 | Author: antant001 | Hits:

[SourceCode] vhdl程序范例

Description:
Platform: | Size: 43233 | Author: miniqiqi07 | Hits:

[VHDL-FPGA-Verilog] VHDL程序范例

Description: 这是有关VHDL的一些范例，可以通过范例学习一点东西，巩固自己学过的东西-This is the VHDL some examples, examples can learn something consolidate learned things
Platform: | Size: 5120 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 用VHDL语言写的，音乐演奏程序，范例歌曲为“青花瓷”片段。-Using VHDL language, and music performance procedures, examples of songs as
Platform: | Size: 700416 | Author: xiezheqi | Hits:

[VHDL-FPGA-Verilog] dianzizhongfangzhen

Description: 8.20 电子时钟VHDL程序与仿真 为初学者提供很好的范例-8.20 electronic clock VHDL program for beginners and simulation provides an excellent example of
Platform: | Size: 59392 | Author: zhangfeng | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: vhdl 范例，很多程序，来源于软件内部-vhdl example
Platform: | Size: 7168 | Author: albertfei | Hits:

[VHDL-FPGA-Verilog] 3

Description: vhdl程序范例，包括测试向量，存储器举例，基本语法，状态机-vhdl program examples, including test vectors, the memory for example, basic grammar, state machine, etc.
Platform: | Size: 183296 | Author: 袁莎莎 | Hits:

[VHDL-FPGA-Verilog] VHDLsample

Description: 英国诺森比亚大学的vhdl语言例程集锦，英文原版。 包含很多优秀的VHDL语言范例，可供学习。所有程序均可在符合IEEE标准的模拟器上模拟。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described in terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can be synthesised using current synthesis tools.
Platform: | Size: 172032 | Author: eensy | Hits:

[Other] Full-Adder

Description: 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
Platform: | Size: 1024 | Author: chenzhang | Hits:

[VHDL-FPGA-Verilog] Example-b8-6

Description: Synplify Pro综合流程序仿真，注：本范例同时提供Verilog和VHDL两种语言版本，请读者根据习惯选用不同的源代码进行操作。-Synplify Pro comprehensive process simulation (note: this example provides two Verilog and VHDL language version at the same time, please choose the different readers according to the habits of the source code.
Platform: | Size: 123904 | Author: 波罗的海 | Hits:

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