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Description: 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
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Size: 4096 |
Author: 明華 |
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Description: 用FPGA设计DSP,2007年上海FPGA高级研修班清华博士贺光辉讲义-FPGA Design with DSP, 2007 in Shanghai FPGA advanced training classes Tsinghua notes Dr. He Guanghui
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Size: 1352704 |
Author: david |
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Description: VHDL Book by Dr Bhaskar
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Size: 1119232 |
Author: jassu |
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Description: E1 Framer/Deframer,E1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate.
Note:This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department / Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi-E1 Framer/Deframer, E1 framer Deframer core implements CCITT (ITU) recommedations G.704, G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note: This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department/Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi
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Size: 139264 |
Author: xiao |
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Description: DDR控制器
- 用XILINX Virtex II FPGA实现
- 使用DDR MT46V16M16作为仿真模型
- 通用化-DR SDRAM Controller Core
- has been designed for use in XILINX Virtex II FPGAs
- works with DDR SDRAM Device MT46V16M16 without changes
- may be easily adapted to any other DDR SDRAM device
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Size: 37888 |
Author: jordanliang |
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Description: This a 4-TAP FIR Filter. This is a VHDL Code that is written by Dr Pooya Torkzadeh.-This is a 4-TAP FIR Filter. This is a VHDL Code that is written by Dr Pooya Torkzadeh.
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Size: 99328 |
Author: emran |
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