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[VHDL-FPGA-Verilogstampsalers

Description: 本压缩包含有一个自动售邮票机,可以选择购买6角,8角的邮票。 可以投入1角,5角,1元的硬币,改程序可实现自动找零,所选邮票面值显示(对应二极管发光),投币不足可以退币-The compression contains a stamp vending machine, you can choose to buy 6 angle, angle of 8 stamps. Should be invested in one angle, 5 angle, one yuan coins to give change process can be achieved automatically, the selected stamp face value of display (corresponding to light-emitting diode), coin shortage of coins can be returned
Platform: | Size: 1024 | Author: 吴明星 | Hits:

[VHDL-FPGA-Verilogalu181

Description: alu运算器vhdl代码,介绍了16中运算方法,可用于cpu的设计中-alu calculator VHDL code, introduction of 16 in computing methods, can be used for the design of cpu
Platform: | Size: 1024 | Author: 赵心 | Hits:

[Graph Recognize61EDA_C1479

Description: 实现人脸识别的代码,是上海交大赵峰老师的实现代码-Achieve face recognition code, Zhao Feng of Shanghai Jiaotong University teachers to achieve code
Platform: | Size: 37900288 | Author: 蔡耀仪 | Hits:

[OtherEngineers_face_Question

Description: 工程师面试题(非常经典,非常全面) 这里面包括数电 模电 VHDL -Engineers face examination questions (very classic, very comprehensive) This includes the number of electric power VHDL model
Platform: | Size: 204800 | Author: 彭府 | Hits:

[VHDL-FPGA-VerilogTIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA

Description: Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.-Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.
Platform: | Size: 28409856 | Author: ramanaidu | Hits:

[VHDL-FPGA-Verilogztj

Description: VHDL 状态机 FPGA编程设计源代码程序你面通通都有-VHDL State Machine Programming FPGA source code program you have them all face
Platform: | Size: 219136 | Author: aya00 | Hits:

[ScannerASM

Description: 按键扫描程序 ASM。1. 键盘采用4*5矩阵键盘,含有两个组合键. 2. 硬件连接比较混乱,且各个按键的排列与面贴上的键码对应混乱.如果采用教科书上常规矩阵键盘的 扫描方式实现比较繁琐. 3. 需要识别两个双键,但这两个双键位置比较特殊K17,K18和K19,K20. 4. 基于2,3两点.这里采用列,行分别输出全零,读取行,列的引脚电平信息.综合这两组信息查表获取键值. 对于单键按下,有两个位为0.对于两个按键按下,有3或4个位为0. -Key scanner ASM. 1. Keyboard with 4* 5 matrix keyboard, with two key combination. 2. Hardware connection is a bit confusing, and the arrangement of the various buttons and paste the key code corresponding to face chaos. If the use of conventional textbooks matrix keyboard scanning more complicated to achieve. 3. need to identify the two double bonds, but the two double bonds are special positions K17, K18 and K19, K20. 4. Based on 2,3 points. here with columns, rows are all zero output , read the rows, columns of pin-level information. comprehensive information look-up table for the two sets of keys. For Speed Press, there are two bits to 0. For the two buttons pressed, 3 or 4 bit to 0.
Platform: | Size: 11264 | Author: dong | Hits:

[VHDL-FPGA-VerilogFACEDECTION

Description: Real times face detection
Platform: | Size: 3072 | Author: Nam | Hits:

[VHDL-FPGA-Verilogface-detection

Description: 基于fpga的人脸识别,包括硬件平台的搭建的详细过程,人脸识别算法的详细程序代码。-Fpga-based face recognition, including the hardware platform to build a detailed process of face recognition algorithm detailed code.
Platform: | Size: 432128 | Author: tiger | Hits:

[VHDL-FPGA-Verilogyoupiao

Description: 使用vhdl语言设计自动售邮票机。用两个发光二极管分别模拟售出面值为6角和8角的邮票,购买者可以通过开关选择一种面值的邮票,灯亮时表示邮票售出。用开关分别模拟1角、5角和1元硬币投入,用发光二极管分别代表找回剩余的硬币。 -Using vhdl language design vending stamp machine. Sold two light-emitting diodes were simulated nominal value of 60 cents and 80 cents stamps, buyers can switch to select a face value of stamps sold stamps lights. Analog switch of 10 cents, 50 cents and 1 yuan coin, with light-emitting diodes represent retrieve the remaining coins.
Platform: | Size: 137216 | Author: 陈小龙 | Hits:

[JSPcaishuzi

Description: VHDL猜数字程序,可以实现猜数字游戏,利用点阵进行倒计时,如果猜对点阵显示笑脸,否则显示X。每一次猜数字利用数码管给出几A几B。设置清空键和开始键。-VHDL guessing programs, you can achieve guessing game, using the dot countdown, if guess the dot matrix display smiley face, otherwise display X. Each Guess the use of digital tube gives a few A few B. Set Clear key and the start key.
Platform: | Size: 2038784 | Author: 玛丽 | Hits:

[Embeded-SCM Developnai_vp62

Description: University of numerical analysis algorithms, Use serial programming examples matlab GUI implementation, Gabor wavelet transform and PCA face recognition code.
Platform: | Size: 5120 | Author: sangqangkaiyun | Hits:

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