Search - VHDL 720

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[Other resource] scaler DL : 0: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。
Update : 2008-10-13 Size : 9.51kb Publisher : wgy
[VHDL-FPGA-Verilog] scaler DL : 0: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Update : 2025-02-17 Size : 9kb Publisher : wgy
[Compress-Decompress algrithms] iqit(verilog) DL : 0: H.264算法中的反变换反量化部分的设计，能够实时处理720x576图像。-The IQIT part of H.264, which can process 720x576 image.
Update : 2025-02-17 Size : 7.71mb Publisher : zyx
[VHDL-FPGA-Verilog] RGB_Control DL : 0: 能将24bit的1080i数据直接存储到fifo中，经过实际的板子验证。还可以通过更改参数改到其他格式，如1080P，720P，720I等。-24bit of 1080i can store data directly to the fifo, the board after the actual verification. Can also be changed by changing the parameters to other formats such as 1080P, 720P, 720I, etc..
Update : 2025-02-17 Size : 2kb Publisher : wwww