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[VHDL-FPGA-Verilog] song DL : 0: module song(clk,key,song_out,led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0] delay reg [7:0] key_reg always @(posedge clk) begin count=count+1 if((count==delay)&(!(delay==20 d65535))) begin count=22 d0 song_reg=!song_reg end end always @(key) begin key_reg=key case(key_reg) 8 b0000_0001: delay=20 d47774 //zhong yin 1 523.3HZ 8 b0000_0010: delay=20 d42568 //zhong yin 2 587.3HZ 8 b0000_0100: delay=20 d37919 //zhong yin 3 659.3HZ 8 b0000_1000: delay=20 d35791 //zhong yin 4 698.5HZ 8 b0001_0000: delay=20 d31888 //zhong yin 5 784HZ 8 b0010_0000: delay=20 d28409 //zhong yin 6 880HZ 8 b0100_0000: delay=20 d25309 //zhong yin 7 987.8HZ 8 b1000_0000: delay=20 d23889 //gao yin 1 1046.5HZ default: delay=20 d65535 endcase end assign song_out=song_reg 文件: song.rar 大小: 357KB 下载: 下载 assign led=key_reg endmodule -module song (clk, key, song_out, led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0 ] delay reg [7:0] key_reg always @ (posedge clk) begin count = count+1 if ((count == delay )& (!( delay == 20' d65535))) begin count = 22 ' d0 song_reg =! song_reg end end always @ (key) begin key_reg = key case (key_reg) 8' b0000_0001: delay = 20' d47774 // zhong yin 1 523.3HZ 8' b0000_0010: delay = 20' d42568 // zhong yin 2 587.3HZ 8' b0000_0100: delay = 20' d37919 // zhong yin 3 659.3HZ 8' b0000_1000: delay = 20' d35791 // zhong yin 4 698.5HZ 8' b0001_0000: delay = 20' d31888 // zhong yin 5 784HZ 8' b0010_0000: delay = 20' d28409 // zhong yin 6 880HZ 8' b0100_0000: delay = 20' d25309 // zhong yin 7 987.8HZ 8' b1000_0000: delay = 20' d23889 // gao yin 1 1046.5HZ default: delay = 20' d65535 endcase end assign song_out = song_reg file: song.rar Size: 357KB Download: Download
Date : 2025-07-04 Size : 357kb User : 罗仲景