Search - VHDL CODE FOR DCT

[2D Graphic] XLIB

Description: 2D图像滤波VHDL代码。 2D图像滤波VHDL代码。-2D image filtering VHDL code. 2D image filtering VHDL code. 2D image filtering VHDL code.
Platform: | Size: 13312 | Author: leisuee | Hits:

[Compress-Decompress algrithms] 601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] dct

Description: 离散余弦变换的verilog源代码，经过验证可实现-Discrete cosine transform of Verilog source code can be verified
Platform: | Size: 27648 | Author: 罗伟 | Hits:

Description: 这个DCT的源代码Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA-The DCT of source code Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA
Platform: | Size: 51200 | Author: lilei | Hits:

[Special Effects] djpeg

Description: 实现jpeg图像解码功能。代码设计思路：1, Reconstruct the Huffman/RLE stream to a sequence 2, Arrange the sequence to a matrix using the zigzag scanning backwards 3, Multiply the matrix by quantization table 􀂄 4, Perform inverse DCT 5, Shift the values by +128 6, Transform back to RGB color space -Realize jpeg image decoding capabilities. Code design: 1, Reconstruct the Huffman/RLE stream to a sequence2, Arrange the sequence to a matrix using the zigzag scanning backwards3, Multiply the matrix by quantization table
Platform: | Size: 186368 | Author: 颜新卉 | Hits:

[VHDL-FPGA-Verilog] dct-code

Description: 离散余弦变换的VHDL实现，不错的代码和方法-Discrete cosine transform VHDL realization of good code and methods
Platform: | Size: 30720 | Author: 宋雪兵 | Hits:

[VHDL-FPGA-Verilog] main_dct

Description: verilog code for dct
Platform: | Size: 2048 | Author: dheeru | Hits:

[VHDL-FPGA-Verilog] xapp610

Description: Verilog code for 2D-DCT with detailed documentation.
Platform: | Size: 128000 | Author: whitestone | Hits:

[Embeded-SCM Develop] MMC-SD

Description: Use PIC18f4550 + MMC and FAT16 with the mikroC, this code is a sample how to use the mmc cards with microcontrollers PIC18f-Use PIC18f4550+ MMC and FAT16 with the mikroC, this code is a sample how to use the mmc cards with microcontrollers PIC18f
Platform: | Size: 84992 | Author: Reinaldo | Hits:

[VHDL-FPGA-Verilog] 1DCT_VHDL

Description: VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.
Platform: | Size: 11264 | Author: NULL | Hits:

[Other] 01

Description: VHDL code for DCT implementation
Platform: | Size: 2048 | Author: Rio Grande | Hits:

« 12 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[2D Graphic] XLIB

[Compress-Decompress algrithms] 601792346200732319490634862

[VHDL-FPGA-Verilog] DCT

[VHDL-FPGA-Verilog] dct

[Graph program] quantizer

[Special Effects] djpeg

[VHDL-FPGA-Verilog] dct-code

[VHDL-FPGA-Verilog] main_dct

[VHDL-FPGA-Verilog] xapp610

[Embeded-SCM Develop] MMC-SD

[VHDL-FPGA-Verilog] 1DCT_VHDL

[mpeg mp3] mpeg2_idct_hw

[VHDL-FPGA-Verilog] verilogdct

[Compress-Decompress algrithms] DCTPROGRAM.ZIP

[VHDL-FPGA-Verilog] attachments_2010_01_29

[VHDL-FPGA-Verilog] two_d_dct_serial

[VHDL-FPGA-Verilog] DCT_IDCT

[VHDL-FPGA-Verilog] dct-partial-code

[VHDL-FPGA-Verilog] JPEG_WEBINAR

[Other] 01

CodeBus www.codebus.net