Search - VHDL CPLD

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[Communication] 用VHDL语言在CPLD_FPGA上实现浮点运算 DL : 0: 用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD / FPGA achieve floating-point computation methods
Update : 2008-10-13 Size : 81.69kb Publisher : wei
[Embeded-SCM Develop] digitalsecondwatch(VHDL) DL : 0: 应用ＶＨＤＬ、ＣＰＬＤ、ＥＤＡ开发软件设计数字系统,能够显著增强设计的灵活性,提高产品的性能,减轻设计的工作量,缩短设计周期。传统的“固定功能集成块+连线”的设计方法正逐步地缩小应用范围,而基于芯片的设计方法正成为电子系统设计的主流。ＶＨＤＬ语言、ＣＰＬＤ/ＦＰＧＡ、ＥＤＡ开发软件已成为设计复杂数字电路系统的重要工具。-use VHDL, CPLD, EDA software to design digital system, can significantly improve design flexibility, improve product performance, reduce the workload designed to shorten the design cycle. The traditional "fixed-function IC Alliance," The design method is to gradually narrow the scope of application, For the chip design is becoming electronic systems design. VHDL, CPLD / FPGA, EDA software development has become a complex digital circuit design system an important tool.
Update : 2008-10-13 Size : 1.42kb Publisher : laiweidong
[VHDL-FPGA-Verilog] whole DL : 0: ov7620的CPLD采集程序，VHDL语言-ov7620 CPLD acquisition procedures, VHDL
Update : 2025-02-17 Size : 1kb Publisher : 韦新峰
[Embeded-SCM Develop] JTAG仿真器CPLD DL : 0: JTAG仿真器CPLD -JTAG Emulator CPLD
Update : 2025-02-17 Size : 337kb Publisher : 李秉
[Embeded-SCM Develop] VHDL Source DL : 0: 无线耳机通讯用CPLD的VHDL源码-wireless headset communications CPLD VHDL source
Update : 2025-02-17 Size : 13kb Publisher : 王阿蒙
[VHDL-FPGA-Verilog] 用VHDL语言在CPLD上实现串行通信 DL : 0: 用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication
Update : 2025-02-17 Size : 4kb Publisher : 陈旭
[Communication] 用cpld实现曼彻斯特编码2 DL : 0: 此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。-this procedure code decoder VHDL hardware is used to prepare the language.
Update : 2025-02-17 Size : 3kb Publisher : 游畅
[VHDL-FPGA-Verilog] CPLD的跑馬燈 DL : 0: cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
Update : 2025-02-17 Size : 63kb Publisher : 口是心非
[Program doc] 用VHDL语言在CPLD_FPGA上实现浮点运算 DL : 0: 用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD/FPGA achieve floating-point computation methods
Update : 2025-02-17 Size : 81kb Publisher : wei
[VHDL-FPGA-Verilog] tbcpu8bit2 DL : 0: 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
Update : 2025-02-17 Size : 201kb Publisher : 冰激凌
[VHDL-FPGA-Verilog] CPLD--VHDL DL : 0: VHDL的基础知识,一切从基础开始!希望这个对大家有所帮助!-VHDL basic knowledge, everything from the foundation started! We hope that the right help!
Update : 2025-02-17 Size : 30kb Publisher : 老纪
[VHDL-FPGA-Verilog] vhdlprogram DL : 0: 用复杂可编程逻辑器件(CPLD)实现的数字钟控系统-with complex programmable logic devices (CPLD) with a digital clock control system
Update : 2025-02-17 Size : 5kb Publisher : 王永
[VHDL-FPGA-Verilog] n_dc_motor DL : 0: vhdl实现的直流电机控制器通用程序对不同fpga/cpld，可能需要修改部分源代码。-VHDL achieved DC Motor Controller General of different procedures they simply/cpld. may need to amend some source code.
Update : 2025-02-17 Size : 2kb Publisher : 刘挺
[VHDL-FPGA-Verilog] Altera_uart_VHDL DL : 0: FPGA/CPLD应用,uart通讯VHDL原码.-FPGA/CPLD applications, UART communications VHDL source.
Update : 2025-02-17 Size : 10kb Publisher : cyberworm
[VHDL-FPGA-Verilog] MVHDL DL : 0: 本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證-the parallel program for controlling flash ROM programs, rom flash can be read out information, After drawing CPLD controller will turn into VESA video signal and output to screen. The program has strong experience card
Update : 2025-02-17 Size : 4.75mb Publisher : 明華
[MPI] 95108325 DL : 0: 通过CPLD实现串行通信之VHDL语言，好看易懂-through CPLD serial communications VHDL, pretty easy to understand
Update : 2025-02-17 Size : 2kb Publisher : dengri
[Other] mcu+CPLD DL : 0: 嵌入式工程师必要的参考材料。mcu 和 CPLD 综合运用 ,有大量实例-Embedded engineers necessary reference material. mcu and comprehensive use of CPLD, a large number of examples
Update : 2025-02-17 Size : 7.59mb Publisher : cruise
[Embeded-SCM Develop] CPLD DL : 0: CPLD初始化程序,用于DSP5416与SAA7111A的时序控制初始化.-CPLD initialization procedure for the DSP5416 and the timing control SAA7111A initialization.
Update : 2025-02-17 Size : 737kb Publisher : 张五一
[Other] cpld-pci DL : 0: 使用 cpld实现pci的功能，思路较为简单方面，希望大家可以测试一下-Use cpld achieve pci functions, a relatively simple idea, the hope that we can test
Update : 2025-02-17 Size : 1kb Publisher : tiantian
[VHDL-FPGA-Verilog] I2C-CPLD DL : 0: I2C总线通讯的CPLD实现，包括详细的设计方法及源程序。-I2C总线通讯的CPLD实现
Update : 2025-02-17 Size : 264kb Publisher : nmh

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