Search - VHDL CUP

[Other] sin_any_w

Description: 用vhdl编写的程序，任意波形产生器，是一年的电子设计大赛赛题，已经实现。-Prepared using VHDL procedures, arbitrary waveform generator is a one-year Electronic Design Competition Cup title, has been achieved.
Platform: | Size: 3790848 | Author: 徐颖 | Hits:

[VHDL-FPGA-Verilog] fftinterface

Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Platform: | Size: 4933632 | Author: 李星 | Hits:

[OA] cpu

Description: 简单的cup程序，帮助初学者学习cpu工作流程，含有仿真波形-Cup simple procedures to help beginners learn cpu workflow, containing simulated waveform
Platform: | Size: 153600 | Author: QWE123 | Hits:

[Other] etester

Description: FPGA实现等精度的频率和脉宽测量，使用次源码的作品获得2008年TI杯湖北省电子设计大赛一等奖-FPGA to achieve such accuracy the frequency and pulse width measurement, the use of sub-source works TI Cup 2008 Electronic Design Competition first prize in Hubei Province
Platform: | Size: 1024 | Author: 冯进伟 | Hits:

[Other] SOPC_EDA

Description: 目录第一章 VHDL文本输入设计方法 1.1 编辑输入并存盘VHDL原文件 1.2 将当前设计设定为工程 1.3 选择VHDL文本编译版本号和排错 1.4 时序仿真 1.5 硬件测试 1.6 部分实验第二章全国大学生电子设计竞赛赛题练习 2.1 等精度频率计设计 2.2 数字移相正弦信号发生器设计 2.3 测相仪设计 2.4 逻辑分析相仪设计 2.5 存储示波器设计-Contents Chapter VHDL design method of text entry Edit 1.1 enter and save the original document VHDL Design 1.2 will present works set to select VHDL version 1.3 compiler version number and troubleshooting 1.4 Timing Simulation 1.5 hardware testing some experimental chapter 1.6 National Undergraduate Electronic Design Cup title race practice, such as precision 2.1 Cymometer 2.2 Designed Digital Phase Shifter Designed Sine Signal Generator 2.3 Design phase measurement logic analysis 2.4 Design 2.5 Design of Storage Oscilloscope
Platform: | Size: 3725312 | Author: 黑月 | Hits:

[VHDL-FPGA-Verilog] traffic_light

Description: 此文件给出了一个多功能交通灯的VHDL代码实现，可作为电赛的准备材料-This paper gives a multi-functional traffic lights to achieve the VHDL code can be used as electric materials Cup preparations
Platform: | Size: 186368 | Author: 王双 | Hits:

[Other] CUP

Description: cup 的设计源代码，含有一步乘除法的功能，在fpja上已经测试过。望对大家有所帮助-cup design source code, which contains step multiplication and division functions in fpja have been tested. We hope to be helpful
Platform: | Size: 870400 | Author: dong | Hits:

[DSP program] FPGADSPBuilder

Description: DE2平台应用及DSPBUILDER技术，是altera杯上海交大电子设计竞赛内部材料，内含详细设计原理及源代码-DE2 platform and DSP BUILDER technology, Shanghai Jiaotong University altera Cup Electronic Design Contest of internal materials, including the principle of the detailed design and source code
Platform: | Size: 3059712 | Author: lucy | Hits:

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[Other] sin_any_w

[VHDL-FPGA-Verilog] fftinterface

[OA] cpu

[Other] etester

[Other] SOPC_EDA

[VHDL-FPGA-Verilog] traffic_light

[Other] CUP

[DSP program] FPGADSPBuilder

[ARM-PowerPC-ColdFire-MIPS] cup

[assembly language] POC

[VHDL-FPGA-Verilog] VHDL

[ARM-PowerPC-ColdFire-MIPS] cpu

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